Dependence of dislocations on emitter phosphorus diffusion conditions and their effects on electrical characteristics of silicon planar NPN transistors

Abstract

It is shown that emitter edge dislocations (EED) need not be “distinct from and in addition to diffusion‐induced dislocations (DID)” as generally accepted. Namely, under certain emitter diffusion conditions, when DID just began to appear, EED and DID can become the same dislocations, originally created inside diffused emitter areas, and then, during emitter oxidation step, displaced towards edges of these areas. Also, it is shown that conventional method for EED elimination, although it considerably reduces a low‐frequency noise of planar NPN transistors, has undesirable effects on the other electrical characteristics: increases reverse emitter‐base current at voltages below avalanche breakdown, i.e. causes “soft” breakdown and reduces commonemitter current gain at low current level.

A probe detector for defectivity assessment in p-n junctions

“…Cigarlike geometry of the probe SPAD; the other layout layers are similar to those already shown in Fig. 1. can move toward the border of the active area [10], [11]. The Wiener diffusion process would mix the clusters of dopant in a wider and wider area, while keeping them always homogeneously scattered into the silicon.…”