A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis

Abstract

Using high-level synthesis techniques, this paper proposes an adaptable high-performance streaming dataflow engine for sparse matrix dense vector multiplication (SpMV) suitable for embedded FPGAs. As the SpMV is a memorybound algorithm, this engine combines the three concepts of loop pipelining, dataflow graph, and data streaming to utilize most of the memory bandwidth available to the FPGA. The main goal of this paper is to show that FPGAs can provide comparable performance for memory-bound applications to that of the corresponding CPUs and GPUs but with significantly less energy consumption. Experimental results indicate that the FPGA provides higher performance compared to that of embedded GPUs for small and medium-size matrices by an average factor of 3.25 whereas the embedded GPU is faster for larger size matrices by an average factor of 1.58. In addition, the FPGA implementation is more energy efficient for the range of considered matrices by an average factor of 8.9 compared to the embedded CPU and GPU. A case study based on adapting the proposed SpMV optimization to accelerate the support vector machine (SVM) algorithm, one of the successful classification techniques in the machine learning literature, justifies the benefits of utilizing the proposed FPGAbased SpMV compared to that of the embedded CPU and GPU. The experimental results show that the FPGA is faster by an average factor of 1.7 and consumes less energy by an average factor of 6.8 compared to the GPU.

Efficient hardware‐accelerated pseudoinverse computation through algorithm restructuring for parallelization in high‐level synthesis

“…This work proposes an optimized algorithm structure for MGS-QRD through loop optimization techniques and algorithm restructuring, improved TMI by eliminating redundant matrix operations and the right choice of matrix multiplication to be integrated into a fast and efficient pseudoinverse computation hardware accelerator on FPGA. FPGA's synthesizable logic fabrics, which allow high parallelism, enable the delivering of high computational speed as demonstrated in some previous works; [6][7][8][9] moreover, it also provides flexibility and programmability with real-time embedded environment solutions. These advantages make FPGA a good potential as a hardware accelerator.…”

An FPGA cached sparse matrix vector product (SpMV) for unstructured computational fluid dynamics simulations

“…The next step consisted of comparing the results with an open library of the SpMV in FPGAs [14]. The library implements a stream version of the SpMV in the traditional CSR format.…”

“…A cache vector strategy was presented in [12] and later utilized in [13], the caching scheme aims at maximizing the data reuse of the multiplying vector by performing a preprocess that determines the cache misses that later work as an input for the algorithm. The cache misses have also been treated by fully transferring the multiplying vector into the BRAM [14]. These works aim to be efficient in a broad set of matrices that does not profit the problem information of the sparsity pattern in our CFD matrices.…”

Energy-efficient algebra kernels in FPGA for High Performance Computing

“…In [18] the authors propose a streaming dataflow architecture to perform SPMV operation in an embedded platform containing a Xilinx ZynqMP FPGA. The proposed solution consists of a deep pipeline that is constantly consuming input data with no stalls.…”

“…For the Xilinx's Data Center platform we tested the GEMM implementation from [14] and developed our version of SPMV based on the work in [18].…”