An FPGA cached sparse matrix vector product (SpMV) for unstructured computational fluid dynamics simulations

Oyarzun, Guillermo; Peyrolon, Daniel; Álvarez, Carlos; Martorell, Xavier

doi:10.48550/arxiv.2107.12371

Cited by 3 publications

(4 citation statements)

References 14 publications

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“…Ref. [1] proposes an FPGA architecture that maximizes the vector's re-usability by introducing a cache-like architecture in which the cache is implemented as a circular list to maintain the BRAM vector components. In Ref.…”

Section: Related Workmentioning

confidence: 99%

“…Sparse matrix-vector multiplication (SpMV) is one of the most important algorithms for solving large sparse linear equations. It is used to solve various practical problems, such as unstructured simulations [1], graph analytics, and machine learning [2]. The time spent on SpMV operations usually accounts for a significant portion of the application runtime.…”

Section: Introductionmentioning

confidence: 99%

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Mapping and Optimization Method of SpMV on Multi-DSP Accelerator

2022

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Sparse matrix-vector multiplication (SpMV) solves the product of a sparse matrix and dense vector, and the sparseness of a sparse matrix is often more than 90%. Usually, the sparse matrix is compressed to save storage resources, but this causes irregular access to dense vectors in the algorithm, which takes a lot of time and degrades the SpMV performance of the system. In this study, we design a dedicated channel in the DMA to implement an indirect memory access process to speed up the SpMV operation. On this basis, we propose six SpMV algorithm schemes and map them to optimize the performance of SpMV. The results show that the M processor’s SpMV performance reached 6.88 GFLOPS. Besides, the average performance of the HPCG benchmark is 2.8 GFLOPS.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Mapping and Optimization Method of SpMV on Multi-DSP Accelerator

2022

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“…Sparse matrix-vector multiplication (SpMV) is a critical operation in a variety of scientific applications such as large simulation systems [1], economic modeling [2], deep learning [3], and more. Optimizing the SpMV kernel on modern hardware devices is highly imperative because SpMV dominates the computing cost in iterative problem-solving methods such as calculating Eigenvalues [4] and Krylov subspace [5].…”

Section: Introductionmentioning

confidence: 99%

Enabling Energy-Efficient and Low-Latency of Sparse Matrix-Vector Multiplication on GPUs

Ashoury,

Loni,

Khunjush

et al. 2023

Preprint

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Sparse matrix-vector multiplication (SpMV) is an essential linear algebra operation that dominates the computing cost in many scientific applications. Due to providing massive parallelism and high memory bandwidth, GPUs are commonly used to accelerate SpMV kernels. Prior studies mainly focused on reducing the latency consumption of SpMV kernels on GPU by tackling the irregular nature of sparse matrices. However, limited attempts have been made to improve the energy efficiency (MFLOPS/Watt) of SpMV kernels, resulting in GPUs being excluded from the range of low-power scientific applications. Furthermore, prior work has primarily focused on optimizing the sparse matrix storage format; the literature ignores evaluating the impact of tweaking compilation parameters (e.g., \texttt{maxrregcount}, thread block size, and such). Lastly, little attention has been paid to preparing a comprehensive training dataset of running SpMV kernels and tweaking the hyperparameters of machine learning-based storage format predictors. To address these limitations, we present a novel learning-based framework, dubbed Auto-SpMV, that enables energy-efficient and low-latency SpMV kernels on GPUs. To achieve the best run time performance, Auto-SpMV proposes two optimization modes: \textit{compile-time} and \textit{run-time}. In the \textit{compile-time} mode, Auto-SpMV tweaks the compilation parameters according to the optimization objective, either lower latency or energy consumption. On the other hand, in the \textit{run-time} mode, Auto-SpMV selects the best sparse format for the input matrix based on an optimized machine learning model. To achieve the best classification results, 1) we collect the largest ever dataset by selecting different sparse matrices running with more than 15K configurations, and 2) we boost classification models by automatically tweaking the learning hyperparameters. Experimental results reveal that Auto-SpMV optimizes latency, energy consumption, average power, and energy efficiency in the \textit{compile-time} mode by up to 51.9%, 52%, 33.2%, and 53%, respectively, compared to the default setting. Auto-SpMV optimizes average power and energy efficiency in the \textit{run-time} mode by up to 34.6% and 99.7%, respectively, compared to the default setting. Finally, our experimental results show that Auto-SpMV generalizes to unseen matrices and hardware devices.

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“…There have been numerous efforts porting incompressible flow calculations to FPGAs. The Himeno benchmark has been used to demonstrate the suitability of FPGAs for this workload [3], and other studies exploring methods for solving equations arising from these systems [4] [5]. By contrast in this work we focus top down on one specific real-world HPC simulation application, namely Alya, and are driven from the perspective of the application developer by the bottlenecks in that code.…”

Section: Introductionmentioning

confidence: 99%

Porting incompressible flow matrix assembly to FPGAs for accelerating HPC engineering simulations

Brown¹

2021

Preprint

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Engineering is an important domain for supercomputing, with the Alya model being a popular code for undertaking such simulations. With ever increasing demand from users to model larger, more complex systems at reduced time to solution it is important to explore the role that novel hardware technologies, such as FPGAs, can play in accelerating these workloads on future exascale systems.In this paper we explore the porting of Alya's incompressible flow matrix assembly kernel, which accounts for a large proportion of the model runtime, onto FPGAs. After describing in detail successful strategies for optimisation at the kernel level, we then explore sharing the workload between the FPGA and host CPU, mapping most appropriate parts of the kernel between these technologies, enabling us to more effectively exploit the FPGA. We then compare the performance of our approach on a Xilinx Alveo U280 against a 24-core Xeon Platinum CPU and Nvidia V100 GPU, with the FPGA significantly out-performing the CPU and performing comparably against the GPU, whilst drawing substantially less power. The result of this work is both an experience report describing appropriate dataflow optimisations which we believe can be applied more widely as a case-study across HPC codes, and a performance comparison for this specific workload that demonstrates the potential for FPGAs in accelerating HPC engineering simulations.

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An FPGA cached sparse matrix vector product (SpMV) for unstructured computational fluid dynamics simulations

Cited by 3 publications

References 14 publications

Mapping and Optimization Method of SpMV on Multi-DSP Accelerator

Mapping and Optimization Method of SpMV on Multi-DSP Accelerator

Enabling Energy-Efficient and Low-Latency of Sparse Matrix-Vector Multiplication on GPUs

Porting incompressible flow matrix assembly to FPGAs for accelerating HPC engineering simulations

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