A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test

Seo, Sungyoul; Cho, Keewon; Lee, Young-Woo; Kang, Sungho

doi:10.1109/jetcas.2018.2833846

Cited by 4 publications

(2 citation statements)

References 41 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The technique in [40] creates partitions and assigns flops using layout information. Then, it uses initial test patterns and performs x-filling to create bit streams with similar values (either 1 or 0).…”

Section: Ordering Chains Using Both Logic Connectivity and Pattern Co...mentioning

confidence: 99%

Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

View full text Add to dashboard Cite

While power reduction during testing is necessary for today's low-power devices, it also lowers test costs. Scan-based methods are the most widely used approach for testing integrated circuits (IC). Test vectors are shifted into and out of scan chains bit by bit during shift operation. The time required for shift operation dominates the test time. With the geometries shrinking (7 nm→5 nm→3 nm→1.8 nm), ICs are required to be tested for newer defects, increasing test time. The most effective way to reduce test time for scan operation is to increase the frequency of the shift operation. Reduction in shift power enables scan operation to be performed with increased frequency, reducing test time, and test cost. This paper presents a survey of techniques proposed recently for shift power reduction. Various techniques, including special flip-flop usage, segmentation, reordering, and low-pass filter, are being reviewed. The techniques are organized based on main attributes to underscore their similarities and differences. Pros and cons in terms of complexities involved in their implementation are discussed. We believe this paper will provide a point of reference for further studies in scan shift power reduction and will be helpful to both industry and academia.

show abstract

Section: Ordering Chains Using Both Logic Connectivity and Pattern Co...mentioning

confidence: 99%

Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

View full text Add to dashboard Cite

show abstract

“…Accordingly, Cui et al described a k-means clustering-based scan chain reordering method under a routing constraint [ 23 ]. Seo et al presented a statistic-based scan chain reordering method that performs scan partitioning to reduce routing overhead [ 24 ]. Huang et al described a routing constrained scan chain reordering technique [ 25 ].…”

Section: Related Workmentioning

confidence: 99%

Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks

Lee

Cho

Kim

et al. 2021

Sensors

Self Cite

View full text Add to dashboard Cite

Cryptographic circuits generally are used for applications of wireless sensor networks to ensure security and must be tested in a manufacturing process to guarantee their quality. Therefore, a scan architecture is widely used for testing the circuits in the manufacturing test to improve testability. However, during scan testing, test-power consumption becomes more serious as the number of transistors and the complexity of chips increase. Hence, the scan chain reordering method is widely applied in a low-power architecture because of its ability to achieve high power reduction with a simple architecture. However, achieving a significant power reduction without excessive computational time remains challenging. In this paper, a novel scan correlation-aware scan cluster reordering is proposed to solve this problem. The proposed method uses a new scan correlation-aware clustering in order to place highly correlated scan cells adjacent to each other. The experimental results demonstrate that the proposed method achieves a significant power reduction with a relatively fast computational time compared with previous methods. Therefore, by improving the reliability of cryptography circuits in wireless sensor networks (WSNs) through significant test-power reduction, the proposed method can ensure the security and integrity of information in WSNs.

show abstract