Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks

Abstract

Cryptographic circuits generally are used for applications of wireless sensor networks to ensure security and must be tested in a manufacturing process to guarantee their quality. Therefore, a scan architecture is widely used for testing the circuits in the manufacturing test to improve testability. However, during scan testing, test-power consumption becomes more serious as the number of transistors and the complexity of chips increase. Hence, the scan chain reordering method is widely applied in a low-power architecture because of its ability to achieve high power reduction with a simple architecture. However, achieving a significant power reduction without excessive computational time remains challenging. In this paper, a novel scan correlation-aware scan cluster reordering is proposed to solve this problem. The proposed method uses a new scan correlation-aware clustering in order to place highly correlated scan cells adjacent to each other. The experimental results demonstrate that the proposed method achieves a significant power reduction with a relatively fast computational time compared with previous methods. Therefore, by improving the reliability of cryptography circuits in wireless sensor networks (WSNs) through significant test-power reduction, the proposed method can ensure the security and integrity of information in WSNs.

Sequential-Fault Diagnosis Strategy for High-Speed Train Traction Systems Based on Unreliable Tests

“…Using design-for-testability (DFT) [7] can make a bus controller work more reliably and stably. One of the methods of DFT is scanning design [8][9][10][11], which can effectively improve the reliability of testing. Testability optimization can address the current shortcomings in the testability of a system by taking appropriate measures via certain means to meet the testability requirements of the system.…”