A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features

Hiromoto, Masayuki; Nakahara, Kohei; Sugano, Hiroki; Nakamura, Yukihiro; Miyamoto, Ryusuke

doi:10.1109/cvpr.2007.383415

Cited by 32 publications

(23 citation statements)

References 9 publications

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“…Also the largest Virtex-5 FPGA was used for the implementation because the design size is too large. Hiromoto et al [15] implemented real-time object detection based on the AdaBoot algorithm. They proposed hybrid architecture of a parallel processing module for the former stages and a sequential processing module for the subsequent stages in the cascade.…”

Section: Introductionmentioning

confidence: 99%

Fpga-based face detection system using Haar classifiers

Cho

Mirzaei

Oberg

et al. 2009

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

121

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This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image scaling, integral image generation, pipelined processing as well as classifier, and parallel processing multiple classifiers to accelerate the processing speed of the face detection system. Also we discuss the optimization of the proposed architecture which can be scalable for configurable devices with variable resources. The proposed architecture for face detection has been designed using Verilog HDL and implemented in Xilinx Virtex-5 FPGA. Its performance has been measured and compared with an equivalent software implementation. We show about 35 times increase of system performance over the equivalent software implementation.

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Section: Introductionmentioning

confidence: 99%

Fpga-based face detection system using Haar classifiers

Cho

Mirzaei

Oberg

et al. 2009

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

121

View full text Add to dashboard Cite

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“…Also, some ad-hoc hardware developments and software implementations for specific architectures different from CPU have been proposed. Masayuki Hirimoto et al studied the requirements of a specialized processor suitable for AdaBoost detection using Haar-like features [9] and Yuehua Shi et al developed a cell array architecture using a multipipeline for speeding up its computation [14]. Some researchers work optimizing the wellknown open source computer vision library OpenCV to run not only under Intel platforms, but also on the Cell BE processor.…”

Section: Motivationmentioning

confidence: 99%

AdaBoost Face Detection on the GPU Using Haar-Like Features

Martínez‐Zarzuela

Pernas

Antón-Rodríguez

et al. 2011

New Challenges on Bioinspired Applications

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Abstract. Face detection is a time consuming task in computer vision applications. In this article, an approach for AdaBoost face detection using Haar-like features on the GPU is proposed. The GPU adapted version of the algorithm manages to speed-up the detection process when compared with the detection performance of the CPU using a well-known computer vision library. An overall speed-up of × 3.3 is obtained on the GPU for video resolutions of 640x480 px when compared with the CPU implementation. Moreover, since the CPU is idle during face detection, it can be used simultaneously for other computer vision tasks.

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“…Also the largest Virtex-5 FPGA was used for the implementation because the design size was too large. Hiromoto et al [19] implemented real-time object detection based on the AdaBoost algorithm. They proposed a hybrid architecture of a parallel processing module for the former stages and a sequential processing module for the subsequent stages in the cascade.…”

Section: B Related Workmentioning

confidence: 99%

Parallelized Architecture of Multiple Classifiers for Face Detection

Cho

Benson

Mirzaei

et al. 2009

2009 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors

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Abstract-This paper presents a parallelized architecture of multiple classifiers for face detection based on the Viola and Jones object detection method. This method makes use of the AdaBoost algorithm which identifies a sequence of Haar classifiers that indicate the presence of a face. We describe the hardware design techniques including image scaling, integral image generation, pipelined processing of classifiers, and parallel processing of multiple classifiers to accelerate the processing speed of the face detection system. Also we discuss the parallelized architecture which can be scalable for configurable device with variable resources. We implement the proposed architecture in Verilog HDL on a Xilinx Virtex-5 FPGA and show the parallelized architecture of multiple classifiers can have 3.3× performance gain over the architecture of a single classifier and an 84× performance gain over an equivalent software solution.

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A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features

Cited by 32 publications

References 9 publications

Fpga-based face detection system using Haar classifiers

Fpga-based face detection system using Haar classifiers

AdaBoost Face Detection on the GPU Using Haar-Like Features

Parallelized Architecture of Multiple Classifiers for Face Detection

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