Fpga-based face detection system using Haar classifiers

Abstract

This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image scaling, integral image generation, pipelined processing as well as classifier, and parallel processing multiple classifiers to accelerate the processing speed of the face detection system. Also we discuss the optimization of the proposed architecture which can be scalable for configurable devices with variable resources. The proposed architecture for face detection has been designed using Verilog HDL and implemented in Xilinx Virtex-5 FPGA. Its performance has been measured and compared with an equivalent software implementation. We show about 35 times increase of system performance over the equivalent software implementation.

A low-power Adaboost-based object detection processor using Haar-like features

“…This module is mainly composed of three OCs so that it can calculate three feature values in one cycle. The integral image update process described in [3] limits input bit width of operators in OC to 17bit and reduces the area of OC. This approach also reduces required bit width for representing each integral image value in a detecting window, which results in eliminating unnecessary flip-flops or multiplexers in the register arrays.…”

“…But the performance of this implementation suffers from limited bandwidth between these memories and a classifier module. In order to obtain high performance characteristics, [3]- [5] employs register arrays to store integral image values, and have multiple classifier modules operated in parallel. However, these architectures do not focus as much on power consumption which is critical for embedded applications.…”

Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs

“…Cho et al [9] proposed an architecture that performed all aspects of the algorithm on the FPGA, using special frame grabbers and buffers to accelerate the calculations. This hardware design, even with the serial portions of the implementation, is substantially faster than conventional processor implementations, operating at 6.55 FPS for VGA images, versus 0.31 FPS for single core implementations [9]. This particular implementation computed 3 features in parallel.…”

“…Design/Author Image Size FPS [5] Unknown 52.00 [6] 120 × 120 15.00 [7] 216 × 288 2.50 [8] 256 × 192 98.00 [9] 640 × 480 6.55 [2] 640 × 480 16.08 [4] 627 × 441 4.30 Table I PREVIOUS ACCELERATED VERSIONS OF VIOLA-JONE'S ALGORITHM A difficulty in comparing the designs in Table I is that not all the designs work with VGA images. Since the processing rate roughly scales linearly with number of image pixels, many of the rates would in fact be far lower if they could be applied to VGA images.…”

FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs

“…Examples range from data parallel kernels [11,13] to entire applications such as face detection [9]. Although they allow flexible customization of the architecture to the application, the physical constraints of their configurable fabric favor certain kernels over others, in terms of performance.…”