A low-power Adaboost-based object detection processor using Haar-like features

Kimura, Masao; Matai, Janarbek; Jacobsen, Matthew; Kastner, Ryan

doi:10.1109/icce-berlin.2013.6697982

Cited by 10 publications

(4 citation statements)

References 5 publications

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“…The detailed comparison to above previous works 22,23,[40][41][42] is shown in Table III, verifying that the architecture proposed in this work can extract all 851 1680-dimensional Haar-like feature vectors in a VGA frame with a shorter processing time of 3.072 ms (i.e., 325 fps frame rate), low power dissipation of 43.45 mW at 120 MHz with 1.8 V supply voltage and smaller memory size of only 96 kbyte (i.e., 12 kB), even though the used CMOS technology is much less advanced.…”

Section: Performance Comparisonmentioning

confidence: 95%

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Low-power coprocessor for Haar-like feature extraction with pixel-based pipelined architecture

Luo

Fujita

et al. 2017

Jpn. J. Appl. Phys.

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Intelligent analysis of image and video data requires image-feature extraction as an important processing capability for machine-vision realization. A coprocessor with pixel-based pipeline (CFEPP) architecture is developed for real-time Haar-like cell-based feature extraction. Synchronization with the image sensor’s pixel frequency and immediate usage of each input pixel for the feature-construction process avoids the dependence on memory-intensive conventional strategies like integral-image construction or frame buffers. One 180 nm CMOS prototype can extract the 1680-dimensional Haar-like feature vectors, applied in the speeded up robust features (SURF) scheme, using an on-chip memory of only 96 kb (kilobit). Additionally, a low power dissipation of only 43.45 mW at 1.8 V supply voltage is achieved during VGA video procession at 120 MHz frequency with more than 325 fps. The Haar-like feature-extraction coprocessor is further evaluated by the practical application of vehicle recognition, achieving the expected high accuracy which is comparable to previous work.

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Section: Performance Comparisonmentioning

confidence: 95%

“…A register-array-based architecture was implemented in Ref. 42. Although it employed the power-optimization techniques of signal-domain gating for integral-image extraction and update, the scheme applied in Ref.…”

Section: Performance Comparisonmentioning

confidence: 99%

Low-power coprocessor for Haar-like feature extraction with pixel-based pipelined architecture

Luo

Fujita

et al. 2017

Jpn. J. Appl. Phys.

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“…In order to quickly and efficiently compute the integral image in embedded systems, specialized hardware solution that consumes less power and area cost is considered to be the best alternative. For the Haar feature based face detection, Kimura [6] proposed a low power architecture and Hiromoto [7] proposed a partial configurable architecture. Both work achieve the integral computing by accumulating the image intensity one by one with the computation complexity of O(m×n), where m and n denote the number of columns and rows in an image, respectively.…”

Section: Introductionmentioning

confidence: 99%

Low-cost and Energy-efficient VLSI Architecture for Fast Integral Image Computing

Xiao¹,

Da²

2017

Proceedings of the 5th IIAE International Conference on Industrial Application Engineering 2017

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This paper proposes a low-cost and energy-efficient VLSI architecture for fast integral image computing. The proposed architecture distributes large size image blocks onto multiple cascaded small size processing units, which enables the comprehensive and fine-grained optimization of the bit width of adders and registers used in the integral image computing. The proposed integral image engine is implemented in RTL and verified on a FPGA-based SoC platform for real-time human face detection. Compared with the state-of-the-art designs, the proposed architecture can reduce up to 33.6% gate count and 31.5% power dissipation.

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“…To enable real time object detection, several Application Specific Integrated Circuit (ASIC) implementations have been proposed [4][5] [6]. Although these implementations can provide powerful computing capability with low power consumption for AdaBoost, cannot offer the required flexibility and programmability.…”

Section: Introductionmentioning

confidence: 99%

Design of an efficient ASIP-based processor for object detection using AdaBoost algorithm

Xiao

Kunieda

et al. 2016

2016 7th International Conference of Information and Communication Technology for Embedded Systems (IC-ICTES)

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Object detection is at the heart of nearly all the computer vision systems. Standard off-the-shelf embedded processors are hard to meet the trade-offs among performance, power consumption and flexibility for future algorithms required by object detection applications. Therefore, this paper presents an Application Specific Instruction set Processor (ASIP) for object detection by using AdaBoost-based learning algorithm with Haar-like features as weak classifiers. In the proposed ASIP, Single Instruction Multiple Data (SIMD) architecture is adopted for fully exploiting data-level parallelism inherent to the target algorithm. With the custom instructions and application-specific registers, the highest computational task within AdaBoost algorithm, which takes almost 80% of the total cycle counts, is accelerated by a factor of 14x compared to the baseline processor.

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A low-power Adaboost-based object detection processor using Haar-like features

Cited by 10 publications

References 5 publications

Low-power coprocessor for Haar-like feature extraction with pixel-based pipelined architecture

Low-power coprocessor for Haar-like feature extraction with pixel-based pipelined architecture

Low-cost and Energy-efficient VLSI Architecture for Fast Integral Image Computing

Design of an efficient ASIP-based processor for object detection using AdaBoost algorithm

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