A source-line programming scheme for low-voltage operation NAND flash memories

Takeuchi, Ken; Satoh, S.; Imamiya, K.; Sakui, Koji

doi:10.1109/4.841463

Cited by 26 publications

(10 citation statements)

References 7 publications

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“…On the other hand, during the program operation, the channels of the program-inhibited (''1''-programming) memory cells should be raised to a program-inhibit voltage, which is typically around 8-10 V, to prevent FN tunneling. [13][14][15][16][17] Normally, the program-inhibit channel voltage is not supplied from the BLs. This is because charging a high voltage to thousands of highly capacitive BLs consumes huge power and takes long set-up time.…”

Section: Tradeoffs In Nand Flash Memory Programmingmentioning

confidence: 99%

“…This is because charging a high voltage to thousands of highly capacitive BLs consumes huge power and takes long set-up time. Instead, self-boosted inhibit scheme [13][14][15] is widely used. It provides the necessary program inhibit voltage even though BLs are only biased to a low supply voltage (for example, 2.5 V).…”

Section: Tradeoffs In Nand Flash Memory Programmingmentioning

confidence: 99%

“…In order to achieve sufficient channel boosting, > 0:6 is required. 15,16) In this paper, channel voltage boosting ratio is evaluated as an index for the channel boosting characteristics rather than the actual V CH during the channel boosting simulation because recent channel boosting schemes are not as simple as the conventional style introduced in x2.1 and depends on each boosting scheme. [13][14][15][16][17] A simplified NAND flash memory string is constructed for both bulk and SOI cells, respectively.…”

Section: Preparationmentioning

confidence: 99%

See 2 more Smart Citations

Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory

Miyaji

Hung

Takeuchi

2012

Jpn. J. Appl. Phys.

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The scaling trends and limitation in sub-20 nm a bulk and silicon-on-insulator (SOI) NAND flash memory is studied by the three-dimensional (3D) device simulation focusing on short channel effects (SCE), channel boost leakage and channel voltage boosting characteristics during the program-inhibit operation. Although increasing punch-through stopper doping concentration is effective for suppressing SCE in bulk NAND cells, the generation of junction leakage becomes serious. On the other hand, SCE can be suppressed by thinning the buried oxide (BOX) in SOI NAND cells. However, the boosted channel voltage decreases by the higher BOX capacitance. It is concluded that the scaling limitation is dominated by the junction leakage and channel boosting capability for bulk and SOI NAND flash cells, respectively, and the scaling limit is decreased to 9 nm using SOI NAND flash memory cells from 13 nm in bulk NAND flash memory cells.

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Section: Tradeoffs In Nand Flash Memory Programmingmentioning

confidence: 99%

Section: Tradeoffs In Nand Flash Memory Programmingmentioning

confidence: 99%

Section: Preparationmentioning

confidence: 99%

See 1 more Smart Citation

Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory

Miyaji

Hung

Takeuchi

2012

Jpn. J. Appl. Phys.

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“…The requirement of low power consumption which is crucial for mobile and green devices has been driving down the operating voltage of NAND flash memory. 1,2) Also, as the NAND flash memory cell is scaled down, endurance and high temperature storage (HTS) characteristics have been regarded as the most important reliability issues of NAND devices [3][4][5][6][7][8][9] and the cell-to-cell interference caused by capacitive coupling has been one of most serious problems for high-density flash memory until now. [10][11][12] However, as NAND devices are scaled down, the degradation of read disturb characteristics will be an important reliability issue for future NAND flash memories.…”

Section: Introductionmentioning

confidence: 99%

Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption

Kang

Park

Song

et al. 2011

Jpn. J. Appl. Phys.

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Two new NAND structures using double common source line (CSL) and dummy switch and their read operation schemes as a solution for NAND flash memories have been proposed. Compared with conventional scheme, the proposed read schemes improves read disturb characteristics beyond sub-30 nm technology node. By using proposed read scheme, the number of fail bits of proposed NAND was decreased than those of conventional NAND at read cycles. Also, it was proven that they contribute to improve the performance and suppress the power consumption. The proposed NAND was verified by both simulation and experimental measurements in a fabricated 40 nm multi level cell (MLC) NAND device.

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“…One of the key issues for low-voltage NAND flash memories is the program disturb problem because the immunity to the program disturb depends greatly on the supply voltage. In [8], a circuit technique has been proposed for high immunity to the disturb with low power consumption. Another key issue for low-voltage NAND flash memory is high-voltage ( ) generation and switching.…”

Section: Introductionmentioning

confidence: 99%

Circuit techniques for a 1.8-V-only NAND flash memory

Tanzawa

Tanaka

Takeuchi

et al. 2002

IEEE J. Solid-State Circuits

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Abstract-Focusing on internal high-voltage () switching and generation for low-voltage NAND flash memories, this paper describes a switch, row decoder, and charge-pump circuit. The proposed nMOS switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the leakage current. The proposed row decoder scheme is described in which all blocks are in selected state in standby so as to prevent standby current from flowing through the proposed switches in the row decoder. A merged charge-pump scheme generates a plurality of voltage levels with an individually optimized efficiency, which reduces circuit area in comparison with the conventional scheme that requires a separate charge-pump circuit for each voltage level. The proposed circuits were implemented on an experimental NAND flash memory. The charge pump and switch successfully operated at a supply voltage of 1.8 V with a standby current of 10 A. The proposed pump scheme reduced the area required for charge-pump circuits by 40%.Index Terms-Charge-pump circuit, high-voltage switching, low supply voltage, NAND flash memories, row decoder.

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A source-line programming scheme for low-voltage operation NAND flash memories

Cited by 26 publications

References 7 publications

Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory

Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory

Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption

Circuit techniques for a 1.8-V-only NAND flash memory

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