A SNDR BIST for \Sigma\Delta Analogue-to-Digital Converters

Rolindez, L.; Mir, Salvador; Bounceur, Ahcène; Carbonero, J.L.

doi:10.1109/vts.2006.12

Cited by 8 publications

(8 citation statements)

References 12 publications

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“…Hence, SiNAD is the ratio of RMS signal power to the noise and distortion power. (4) where A signal (rms) is the RMS output signal level and A noise+distortion is the RMS sum of all spectral components below the Nyquist frequency, excluding DC. ENOB is a measure of the resolution of the converter compared to the ideal resolution of the converter (in LSBs) and can be written in terms of SiNAD.…”

Section: Sinad and Enobmentioning

confidence: 99%

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Low Cost Dynamic Test Methodology for High Precision ΣΔ ADCs

Kook

Choi

Natarajan

et al. 2009

2009 Asian Test Symposium

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1 : In this paper, a low-cost test methodology for dynamic specifications of high precision sigma-delta (∆Σ) analog-to-digital converters (ADCs) is presented. Dynamic testing of ADCs requires an input test stimulus with total harmonic distortion (THD) and signal-to-noise ratio (SNR) about 10dB better than the ADC under test. ∆Σ ADCs are inherently high resolution converters with excellent THD and SNR due to their inherent oversampling, averaging and noise shaping properties. In the proposed test methodology, the back end digital and decimation filters of such converters are turned off and the digital pulse sequence at the output of the sigma-delta modulator is made externally observable for test purposes. It is seen that ENOB, THD and SNR of the converter can be determined with significantly increased sensitivity to device nonlinearities and noise allowing the use of less than ideal input stimulus than otherwise or significantly reduced test time. The back-end filters are then tested using traditional digital test techniques. Simulation results show the usefulness of the proposed test methodolgy.

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Section: Sinad and Enobmentioning

confidence: 99%

“…Use of digital signal stimulus for testing sigma-delta converters was proposed in [1]- [4]. Similar digital stimulus generated by software is presented in [2] and [3].…”

Section: Introductionmentioning

confidence: 99%

Low Cost Dynamic Test Methodology for High Precision ΣΔ ADCs

Kook

Choi

Natarajan

et al. 2009

2009 Asian Test Symposium

View full text Add to dashboard Cite

show abstract

“…Aiming at reducing the complexity of the sine-wave fitting algorithm, we have proposed in [17] to reuse the digital decimation filter already existing in the converter to generate a reference signal synchronized with the output response. This strategy reduces the digital overhead area, but we still need a memory to save both signals: output response and reference signal.…”

Section: International Test Conferencementioning

confidence: 99%

“…Figure 2 shows the spectrum of the 2252-bit stream used as stimulus in the BIST mode. This stimulus is obtained by the periodical reproduction of an optimized binary train recorded from the output of a software 3 rd order Σ∆ modulator [17]. When we clock this stimulus at the sampling frequency, the test signal is at f stimulus = f sampling /2252 = 5456 Hz, with the first three harmonics (10912 kHz, 16369 Hz and 21825 Hz) falling in the audio bandwidth.…”

mentioning

confidence: 99%

A stereo audio Σ∑ ADC architecture with embedded SNDR self-test

Rolindez

Mir

Carbonero

et al. 2007

2007 IEEE International Test Conference

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In this paper we present a new architecture for audio Analog-to-Digital Converters (ADCs) that includes a Built-In Self-Test (BIST) technique for the test of the Signal-to-Noise and Distortion Ratio (SNDR). A periodical binary stream is generated in the chip in order to stimulate the converter. The reuse of the bandgap circuit already existing in the converter allows us to generate the test stimulus with a very small analog area overhead. The output response analysis is performed by means of a sinewave fitting algorithm. The reuse of the digital filter already existing in the converter allows us to generate a synchronized reference signal necessary for the fitting algorithm. The BIST technique is equivalent to a standard test carried out with a sinusoidal signal at -12 decibels Full-Scale (dBFS). The total test time is 60 ms and the estimated BIST overhead area is 7.5% of the whole stereo converter area in a 0.13 µm CMOS technology. Experimental results show that the correlation between the embedded self-test and a sinusoidal standard test is excellent, with a SNDR error smaller than 1 dB. IntroductionIn order to satisfy the rising demand for high quality audio devices, the performances of Sigma-Delta Analog-toDigital Converters (Σ∆ ADCs) are continuously improving with larger modulator bandwidths and higher dynamic ranges. As the performances of these circuits increase, its test is in turn more difficult and costly. Built-In Self-Test (BIST) techniques can reduce this cost by integrating the test approach in the design phase.In the last years, an intense research effort has been carried out in order to find BIST solutions for ADCs. The Oscillation-based Built-In Self-Test (OBIST) was proposed in [1] for the calculation of the input transition voltages and non-linearity errors. The main advantage of this method is that we do not need to generate an analog input stimulus for the test. However, it does not measure dynamic parameters and it takes a long test time for high-resolution converters. The oscillation-based BIST has also been applied to the test of Σ∆ modulators [2], where the modulator is reconfigured to be an oscillator. Both the frequency and the amplitude of the oscillation are measured in order to separate faulty-circuits from faultfree ones. The need to modify the circuit and the sensibility to process variations can deteriorate the quality of this BIST approach.Other authors [3,4,5,6] have proposed the estimation of the leakage in the modulator integrators, which is directly related to the quantization noise present in the bandwidth of the modulator at its output. Additionally, the same approach is used in [6] for the estimation of the settlingtime. These approaches do not allow for a complete validation of the modulator and additional tests may be necessary. Furthermore, in [3] and [4] large digital resources are required.The histogram-based technique has also been applied to the BIST of ADCs in [7]. However, only static information is obtained and long test times are necessary when the number of ...

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“…In [1]- [4] the authors propose the use of digital signal stimulus for testing sigma-delta converters. However, the use of on-chip digital stimulus generation resources and the analysis of large bit-streams of data are necessary.…”

Section: Introductionmentioning

confidence: 99%

Signature Testing and Diagnosis of High Precision S? ADC Dynamic Specifications Using Model Parameter Estimation

Kook

Banerjee

Chatterjee

2011

2011 Sixteenth IEEE European Test Symposium

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1 : Dynamic testing of high-resolution SigmaDelta (∆Σ) Analog-to-Digital converters (ADCs) is extremely challenging and expensive since it requires the use of spectrally pure stimulus with at least 10dB better signal-to-noise ratio (SNR) and total harmonic distortion (THD) than the ADC under test. This paper presents a low cost model parameter estimation based test and diagnosis methodology for the dynamic specifications of highprecision ∆Σ ADCs using a multi-tone test input. In the proposed test methodology, the response of a behavioral model of the ADC incorporating its key module level nonidealities is matched with the response of the ADC under test by solving a nonlinear optimization problem that finds the best non-ideality parameters corresponding to the observed DUT test response. The dynamic specifications of the ADC are then calculated from the derived model parameters. The multi-tone test stimulus is designed in such a way as to maximize the accuracy with which the model non-ideality parameters can be calculated from the observed test response using a genetic test stimulus optimization algorithm. For test response analysis, the digital pulse sequence at the output of the sigma-delta modulator is made externally observable and utilized as a test access point. A key contribution is that the dynamic specifications such as ENOB, SNR, and THD of the converter as well as module level non-idealities contributing to those specifications can be simultaneously determined from the derived model parameters. The test method is fast and diagnosis is very accurate. Simulation results indicate the validity of the proposed methodology.

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A SNDR BIST for \Sigma\Delta Analogue-to-Digital Converters

Cited by 8 publications

References 12 publications

Low Cost Dynamic Test Methodology for High Precision ΣΔ ADCs

Low Cost Dynamic Test Methodology for High Precision ΣΔ ADCs

A stereo audio Σ∑ ADC architecture with embedded SNDR self-test

Signature Testing and Diagnosis of High Precision S? ADC Dynamic Specifications Using Model Parameter Estimation

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A SNDR BIST for \Sigma\Delta Analogue-to-Digital Converters

Cited by 8 publications

References 12 publications

Low Cost Dynamic Test Methodology for High Precision &#x03A3;&#x0394; ADCs

Low Cost Dynamic Test Methodology for High Precision &#x03A3;&#x0394; ADCs

A stereo audio &#x03A3;&#x2211; ADC architecture with embedded SNDR self-test

Signature Testing and Diagnosis of High Precision S? ADC Dynamic Specifications Using Model Parameter Estimation

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Product

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Low Cost Dynamic Test Methodology for High Precision ΣΔ ADCs

Low Cost Dynamic Test Methodology for High Precision ΣΔ ADCs

A stereo audio Σ∑ ADC architecture with embedded SNDR self-test