A simple and efficient method for generating compact IDDQ test set for bridging faults

Shinogi, Tsuyoshi; Hayashi, T.

doi:10.1109/vtest.1998.670857

Cited by 12 publications

(4 citation statements)

References 12 publications

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“…All test points data would be collected per device under test (DUT) during the DUT testing and then calculated and analyzed on-site based on linear regression model (9) for The lower limits were defined by Tlower = Minmeas, assume -Outlier [2] The outliers were confirmed based on post statistical analysis done at preproduction stage which was 130nm products scenario. For the products fabricated in 65nm, the combination of current ratios and delta IDDQ techniques are adopted.…”

Section: Iddq Measurements Statistical Analysis and Manufacturing Imp...mentioning

confidence: 99%

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IDDQ Test Practice in Nanotechnologies

Ye¹,

Shen²,

Liu³

et al. 2011

ECS Trans.

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As semiconductor wafer process technology went into nanotech level, IDDQ test faced tremendous challenges than it ever did due to high intrinsic leakage. A case study of IDDQ test in Availink ASICs in 130nm and 65nm process technologies demonstrates that IDDQ test is still feasible. The scheme includes IDDQ test vectors precise selection/generation, IDDQ measurement with high resolution /repeatability, proper statistical post processing algorithm in outlier detection, results verification, etc. As a result, IDDQ test is still considerable in manufacturing test strategy in nanotechnologies era.

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Section: Iddq Measurements Statistical Analysis and Manufacturing Imp...mentioning

confidence: 99%

“…IDDQ testing offers several advantages. Since the supply current can be monitored easily, it provides excellent observability (2). Only a few vectors are usually enough to achieve reasonable high fault coverage.…”

Section: Introductionmentioning

confidence: 99%

IDDQ Test Practice in Nanotechnologies

Ye¹,

Shen²,

Liu³

et al. 2011

ECS Trans.

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“…As a result, a test vector which detects no essential faults becomes redundant, and it is removed. Iterative improvement by changing one bit has been proposed in [30]. This technique is simple and easy to implement.…”

Section: Test Compactionmentioning

confidence: 99%

Fault models and test generation for IDDQ testing

Higami

Takamatsu²,

Saluja³

et al.

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)

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Abstract| This paper surveys recent research related to IDDQ testing, particularly focuses on fault models and test generation methods.(1) The paper provides a taxonomy of fault models that have been studied in literature, and classies these models into a small set of faults.(2) The paper describes ecient test generation methods and fault simulation methods. Test compaction methods, including reduction of the total number of test vectors and selection of IDDQ measurement v ectors, are also described.

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“…For bridging faults, dynamic test compaction procedures for I DDQ testing were described in [16]- [18]. In this work, we describe a test compaction procedure for bridging faults in full-scan circuits under voltage testing.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Test Compaction for Bridging Faults

Pomeranz

Reddy

Sixth International Symposium on Quality of Electronic Design (ISQED'05)

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We describe a dynamic test compaction procedure for four-way bridging faults. Under this fault model, a pair of lines g i ,g j is associated with four bridging faults corresponding to two possible combinations of opposite values on g i and g j , and two options for the line whose value is faulty in the presence of the fault (either g i or g j ). Compaction is achieved by simultaneously considering faults that have a line g i with a value α i in common, such that the value α i on g i is affected by the presence of the fault. Faults with a common line g i and value α i differ only in the second line g j of each pair of bridged lines, and the second lines only need to be assigned the value α i in order to detect all the faults. This strong relationship between the faults allows us to derive tests that detect large numbers of these faults, resulting in compact test sets.

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A simple and efficient method for generating compact IDDQ test set for bridging faults

Cited by 12 publications

References 12 publications

IDDQ Test Practice in Nanotechnologies

IDDQ Test Practice in Nanotechnologies

Fault models and test generation for IDDQ testing

Dynamic Test Compaction for Bridging Faults

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