As semiconductor wafer process technology went into nanotech level, IDDQ test faced tremendous challenges than it ever did due to high intrinsic leakage. A case study of IDDQ test in Availink ASICs in 130nm and 65nm process technologies demonstrates that IDDQ test is still feasible. The scheme includes IDDQ test vectors precise selection/generation, IDDQ measurement with high resolution /repeatability, proper statistical post processing algorithm in outlier detection, results verification, etc. As a result, IDDQ test is still considerable in manufacturing test strategy in nanotechnologies era.
With diagnosis tools' help, people analyze the yield problem and identify the process issues and finally improve production yield rate. Nowadays, this approach is often employed during products initial ramping up stage in foundry and large chip design house. It is not often to see that people apply diagnosis-driven analysis for matured products, capture the root causes, especially after wafer foundry confirmed their process control within target.We would like to introduce a case study for matured SoC product low yield analysis. With scan diagnosis and layout aware diagnosis, we apply all possible analysis and identify FA candidates for PFA (physical failure analysis), then capture process issues, and then finally enhance the yield with foundry process control. As a result for evidence captured, wafer foundry gives the compensation for the yield loss due to process control leak.
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