With diagnosis tools' help, people analyze the yield problem and identify the process issues and finally improve production yield rate. Nowadays, this approach is often employed during products initial ramping up stage in foundry and large chip design house. It is not often to see that people apply diagnosis-driven analysis for matured products, capture the root causes, especially after wafer foundry confirmed their process control within target.We would like to introduce a case study for matured SoC product low yield analysis. With scan diagnosis and layout aware diagnosis, we apply all possible analysis and identify FA candidates for PFA (physical failure analysis), then capture process issues, and then finally enhance the yield with foundry process control. As a result for evidence captured, wafer foundry gives the compensation for the yield loss due to process control leak.
In complex SoC design, the higher performance and compact package would often cause tremendous problems with signal integrity - simultaneous switching noise issues, crosstalk issues, and resonance issues. Therefore, to design the chip, the package and its system concurrently can draw out all critical constraints simultaneously to all parties (chip, package and system design teams). In the process, a single interactive database is essential to allow design teams perform high speed interconnect analysis at both physical and electrical levels and make optimization tradeoffs among all levels. Meanwhile, the methodology also supports collaborative designs among fabless design house, package house and printed circuit board design suppliers. A case study of Availink SoC package and system board design listed the issues faced and explored the methodology described above and compared both critical signals simulation and physical test results. Finally a general flow of concurrent and collaborative design with simple analysis, as a comparison to conventional way, is given.
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