Fault models and test generation for IDDQ testing

Higami, Yoshinobu; Takamatsu, Yasushi; Saluja, Kewal K.; Konshita, K.

doi:10.1109/aspdac.2000.835152

Cited by 4 publications

(5 citation statements)

References 30 publications

(58 reference statements)

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“…An ATPG algorithm decides testability of a PSF and returns a test vector for a testable fault. Additional fault models are typically used for IDDQ testing [10], the extension of the algorithms presented here is straightforward.…”

Section: Preliminariesmentioning

confidence: 99%

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Deterministic Algorithms for ATPG under Leakage Constraints

Fey

2009

2009 Asian Test Symposium

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Abstract-Measuring the steady state leakage current (IDDQ) is very successful in detecting faults not discovered by standard fault models. But vector dependencies of IDDQ decrease the resolution.We propose deterministic ATPG algorithms to create test vectors within predefined leakage ranges. Even when random pattern generation does not find test vectors, the proposed algorithms identify vectors within the desired range. Experimental results confirm that leakage constraints are effectively handled during test pattern generation without decreasing fault coverage.Keywords-Algorithms, deterministic ATPG, IDDQ I. INTRODUCTIONThe steady state leakage current (IDDQ) is a good indicator to decide whether a circuit contains failures introduced during production. Even faults that remain undiscovered using functional testing based on fault models are detected by IDDQ measurements [1].With continuously shrinking feature sizes the IDDQ current of devices increases. At the same time the IDDQ current of good devices changes due to process variations and test vector dependencies. Consequently, differentiating good and bad devices by using a simple threshold value for the IDDQ current becomes infeasible.Instead, post-processing techniques are typically applied to handle IDDQ variations. Current signatures [2] are a sorted plot of measured IDDQ values. Discontinuities in this curve typically indicate a fault. Delta-IDDQ [3] is an improvement that compares the differences between measurements and yields more accurate information. These techniques and similar approaches [4] help to remove certain effects coming from process variations and from test vector dependencies.In contrast to these approaches the technique of [5] is applied before the measurement during Automatic Test Pattern Generation (ATPG). By this, leakage variations coming from test vector dependencies are drastically reduced. An IDDQ model predicts the expected leakage current for a given test vector. Then, a small range for IDDQ is defined. Only test vectors within this range are created by the ATPG tool. Figure 1 shows the resulting leakage signatures. No restrictions (α = ∞) yield test vectors across a wide range of leakage values. Tight restrictions (α = 0.5) yield an almost linear curve with a small slope while keeping high fault coverage. Consequently, good and bad devices can be differentiated more easily by IDDQ testing. But no complete ATPG algorithm was given, instead a simple heuristic was applied to generate test vectors. That approach cannot decide whether no test vector within the defined range exists.Algorithms for input vector control [6], [7], [8] search for the input assignment causing the lowest quiescent current for a circuit. Thus, a single optimization problem is solved.

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Section: Preliminariesmentioning

confidence: 99%

“…The same step calculates the leakage current of t by event based simulation as discussed below. If the vector is within the range, the fault is testable (10). Otherwise, the next extension is considered.…”

Section: Integrating Atpg and Simulation-based Iddq Estimationmentioning

confidence: 99%

Deterministic Algorithms for ATPG under Leakage Constraints

Fey

2009

2009 Asian Test Symposium

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“…The survey in [8] provides an overview of additional fault models and fault extraction techniques used in IDDQ testing.…”

Section: Fault Modelmentioning

confidence: 99%

“…These approaches mainly address issues of fault extraction and fault modeling [9]. Once the faults are modeled only constraints due to the logic function of the circuit are considered during ATPG [9,2,8,12]. As a result the leakage current may vary significantly from one test vector to the next due to the dependency of the leakage current on the internal state of a circuit.…”

Section: Introductionmentioning

confidence: 99%

Targeting Leakage Constraints during ATPG

Fey

Komatsu

Furukawa

et al. 2008

2008 17th Asian Test Symposium

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In previous technology generations IDDQ testing used to be a powerful technique to detect physical faults that are not covered by standard fault models or functional tests. Due to shrinking feature sizes and consequently increasing leakage currents IDDQ testing becomes difficult in the deep-submicron area. One of the problems is the vector dependency of leakage current. Even in good devices the leakage current may vary significantly from one test vector to the next.In this work we present an ATPG framework that allows to generate test vectors within tight constraints on leakage currents. The target range for the leakage current is automatically determined. Experiments on the ITC99 benchmark suite yield testsets that achieve 100% fault coverage for the larger circuits, even when the range is narrowed down to 50% of the standard deviation of random vectors.

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“…It is well known that IDDQ testing, which measures quiescent power supply current (denoted by IDDQ), is efficient for CMOS circuits [45][46][47][48]. Since in IDDQ testing, unlike logic testing, faulty effects do not need to be propagated to primary outputs, test generation for IDDQ testing is easier than logic testing.…”

Section: Test Compaction For Iddq Testingmentioning

confidence: 99%

Test cost reduction for logic circuits: Reduction of test data volume and test application time

Higami

Kajihara

Ichihara

et al. 2005

Systems & Computers in Japan

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SUMMARYWe believe that reduction of the testing cost is becoming increasingly important as the size of VLSIs becomes larger. Moreover, as the structure of VLSIs becomes more complicated, test compaction, test compression, and test application time reduction for non-stuck-at faults, such as delay faults, bridging faults, crosstalk faults, and open faults, must be considered. In addition, new methods of fault diagnosis and high-level testing must be developed in order to reduce testing costs or diagnostic costs. In this paper we have surveyed recent research on the reduction of testing cost for logic circuits, including test compaction for combinational circuits and sequential circuits, test compaction under IDDQ testing, and test compression and test application time reduction for scan circuits.

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Fault models and test generation for IDDQ testing

Cited by 4 publications

References 30 publications

Deterministic Algorithms for ATPG under Leakage Constraints

Deterministic Algorithms for ATPG under Leakage Constraints

Targeting Leakage Constraints during ATPG

Test cost reduction for logic circuits: Reduction of test data volume and test application time

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