A Significant Shift of Schottky Barrier Heights at Strongly Pinned Metal/Germanium Interface by Inserting an Ultra-Thin Insulating Film

Nishimura, Tomonori; Kita, Koji; Toriumi, Akira

doi:10.1143/apex.1.051406

Cited by 222 publications

(170 citation statements)

References 14 publications

(15 reference statements)

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“…Hence, we have demonstrated two kinds of tuning methods for the metal wave function tail into Ge. One is ultrathin-film insertion, which can block the tailing, 9) and the other is the electron density modulation in metals, which may change the tailing extent into Ge. Since the density of MIGS at element metal=Ge should be sufficiently high to screen out other extrinsic FLP mechanisms, the strong intrinsic mechanism should dominate the FLP.…”

mentioning

confidence: 99%

Reexamination of Fermi level pinning for controlling Schottky barrier height at metal/Ge interface

Nishimura

Yajima

Toriumi

2016

Appl. Phys. Express

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The element metal/germanium (Ge) interface exhibits a strong Fermi level pinning (FLP), which is usually characterized on the basis of Ge side semiconductor properties. In this work, we demonstrate that metal properties significantly affect the Schottky barrier height (SBH) on Ge. Metallic germanides show both FLP alleviation and a clear substrate orientation dependence of SBH on Ge, despite the nearly perfect FLP and very slight orientation dependence in the element metal case. As a result, ohmic characteristics are observed at germanide/n-Ge (111) junctions. The metal properties required to alleviate the FLP on Ge are also discussed. © 2016 The Japan Society of Applied Physics G ermanium (Ge) is one of the promising semiconductor materials for high-performance complementary metal-oxide-semiconductors (CMOSs) in the next generation owing to its high electron and hole mobilities. Recently, high electron mobility in Ge n-channel metal-insulation-semiconductor field-effect transistors (n-MISFETs) with a sub-nm equivalent oxide thickness gate stack has been demonstrated, owing to appropriate gate stack designing, [1][2][3][4] in addition to the high hole mobility in Ge p-MISFET, which has already been reported. 5,6) Therefore, the most serious challenges for realizing practical scaled Ge CMOS are currently the reduction in parasitic resistance and the suppression of off-state leakage at the source=drain of MISFETs. In particular, to reduce the contact resistance at the metal=Ge interface, a reduction in Schottky barrier height (SBH) at the interface is definitely required. However, the Fermi level is almost perfectly pinned to the valence band edge of Ge at the metal=Ge interface for various element metals. 7,8) This fact suggests that the Fermi level pinning (FLP) on Ge may be limited by an intrinsic mechanism. Therefore, understanding the FLP mechanism and controlling the SBH on n-Ge are strongly required.Recently, FLP alleviation has been demonstrated in ultrathin-film [GeO 2 , 9) Al 2 O 3 , 9) GeN, 10) SiN,11) MgO,12) Si,13) ZnO, 14) TiO 2 , 15) W-encapsulating Si, 16) indium tin oxide (ITO) 17) ] insertion at the element metal=Ge interface. When the direct metal=Ge interface is replaced by the metal= ultrathin film and ultrathin film=Ge interfaces, the strong FLP at the direct metal=Ge interface becomes less significant. Nevertheless, since the interface layer resistance is added, the direct metal=Ge interface with a low SBH is more preferable from the viewpoint of contact resistance reduction. With respect to the direct metal=Ge interface, it has recently been reported that the SBHs at epitaxial Fe 3 Si, 18) α-TiGeN, 19) epitaxial Mn 5 Ge 3 , 20) epitaxial NiGe 2 , 21) graphene, 22) and Sn 23) =n-Ge interfaces are relatively low, which deviates from the trend of strong FLP. 7,8) Some of them 18,20,21,23) considered that the FLP on Ge might not be determined by an intrinsic but extrinsic origin. It is inferred that those two kinds of experimental results may include a key aspect to understand the FLP mechani...

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mentioning

confidence: 99%

Reexamination of Fermi level pinning for controlling Schottky barrier height at metal/Ge interface

Nishimura

Yajima

Toriumi

2016

Appl. Phys. Express

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“…Several studies examine the effect of the proximity of the metal atoms to the metal-semiconductor interface and the generation of metal-induced gap states (MIGS) [105,57,106,107]. The work presented here aims to examine the effect of ultra-thin layers of chromium with a pinning effect generated from the gold capping layer.…”

Section: Fermi Level Pinningmentioning

confidence: 99%

“…Previous studies on Fermi-level pinning reveal that MIGS can be generated by a metal layer several atomic distances away from the interface. Nishimura et al investigated germanium with ultra-thin oxides at the interface and various metals on top of the oxide [105]. While varying the oxide thickness Nishimura was able to change the electrical properties of the diode from ohmic transport to Schottky and from Schottky to ohmic.…”

Section: Fermi Level Pinningmentioning

confidence: 99%

Nanoscale Schottky barrier visualization utilizing computational modeling and ballistic electron emission microscopy

Nolting

Durcan

Gassner

et al. 2018

Journal of Applied Physics

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The electrostatic barrier at a metal semiconductor interface is visualized using nanoscale spatial and meV energetic resolution. A combination of Schottky barrier mapping with ballistic electron emission microscopy and computational modeling enables extraction of the barrier heights, the hot electron scattering, and the presence of localized charges at the interface from the histograms of the spectra thresholds. Several metal semiconductor interfaces are investigated including W/Si(001) using two different deposition techniques, Cr/Si(001), and mixed Au-Ag/Si(001). The findings demonstrate the ability to detect the effects of partial silicide formation in the W and Cr samples and the presence of two barrier heights in intermixed Au/Ag films upon the electrostatic barrier of a buried interface with nanoscale resolution. This has potential to transform the fundamental understanding of the relationship between electrostatic uniformity and interface structure for technologically important metal semiconductor interfaces.

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“…1,2 By simply inserting an ultrathin dielectric layer-such as TiO x , 3-8 AlO x , [9][10][11] Si 3 N 4 , 9,12,13 MgO, 14,15 etc. [16][17][18][19][20] -between the metal and the semiconductor, / b can be efficiently lowered down to 0.2 eV or even further.…”

Section: Contact Resistivities Of Metal-insulator-semiconductor Contamentioning

confidence: 99%

“…The advantage of the MIS contacts is most pronounced at relatively low doping levels, but it diminishes gradually with increasing N d -at ultrahigh doping levels, even the "ideal" MIS, A, cannot outperform its MS counterpart, D. Moreover, the existence of such an "ideal" MIS as A is suspicious: for instance, insulators with m Ã ti as low as 0.2 m 0 are uncommon; 46,50 insulators that have low DE C with semiconductors are rare; 44,46,50 moreover, there is usually a minimal insulator thickness of >1 nm required for an MIS to lower / b to 0.1 eV. 5,7,9,13 In conclusion, the MIS contacts are more appealing to the applications that use relatively low doped semiconductors, such as compound semiconductor devices and Si solar cells, while the MS contacts will still be the major force to push q c down below 1 Â 10 À8 XÁcm 2 to meet the Complementary Metal-Oxide-Semiconductor (CMOS) requirement for the 10 nm technology node and beyond. 51 In summary, this paper systematically compares the contact resistivity of the MIS and MS contacts.…”

Section: Contact Resistivities Of Metal-insulator-semiconductor Contamentioning

confidence: 99%

Contact resistivities of metal-insulator-semiconductor contacts and metal-semiconductor contacts

Schaekers

Barla

Horiguchi

et al. 2016

Applied Physics Letters

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Applying simulations and experiments, this paper systematically compares contact resistivities (ρc) of metal-insulator-semiconductor (MIS) contacts and metal-semiconductor (MS) contacts with various semiconductor doping concentrations (Nd). Compared with the MS contacts, the MIS contacts with the low Schottky barrier height are more beneficial for ρc on semiconductors with low Nd, but this benefit diminishes gradually when Nd increases. With high Nd, we find that even an “ideal” MIS contact with optimized parameters cannot outperform the MS contact. As a result, the MIS contacts mainly apply to devices that use relatively low doped semiconductors, while we need to focus on the MS contacts to meet the sub-1 × 10−8 Ω cm2 ρc requirement for future Complementary Metal-Oxide-Semiconductor (CMOS) technology.

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A Significant Shift of Schottky Barrier Heights at Strongly Pinned Metal/Germanium Interface by Inserting an Ultra-Thin Insulating Film

Cited by 222 publications

References 14 publications

Reexamination of Fermi level pinning for controlling Schottky barrier height at metal/Ge interface

Reexamination of Fermi level pinning for controlling Schottky barrier height at metal/Ge interface

Nanoscale Schottky barrier visualization utilizing computational modeling and ballistic electron emission microscopy

Contact resistivities of metal-insulator-semiconductor contacts and metal-semiconductor contacts

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