A self-testing 2-μm CMOS chip set for FFT applications

Fox, Josef J.; Surace, G.; Thomas, P.A.

doi:10.1109/jssc.1987.1052665

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Cited by 7 publications

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“…The use of one ROM for each butterfly processor is recommended [1]. In the conventional approach, N/r twiddle factors are stored [2][3][4][5][6], being r the used radix. Some authors have used trigonometric properties to reduce the coefficient memory to a half [7][8][9], in this case, only coefficients on the first quadrant of the unit circle are stored.…”

Section: Introductionmentioning

confidence: 99%

Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs

Sansaloni

Perez-Pascual

Torres

et al. 2007

J VLSI Sign Process Syst Sign Image Video Technol

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A scheme for reducing the hardware resources to implement on LUT-based FPGA devices the twiddle factors required in Fast Fourier Transform (FFT) processors is presented. The proposed scheme reduces the number of embedded block RAM for large FFTs and the number of slices for FFT lengths higher than 128 points. Results are given for Xilinx devices, but they can be generalized for other advanced LUT-based devices like ALTERA Stratix.

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