Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs

Sansaloni, T.; Perez-Pascual, A.; Torres, V.; Valls, Javier

doi:10.1007/s11265-007-0055-8

Cited by 7 publications

(5 citation statements)

References 12 publications

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“…Most of the researchers studied on twiddle factors to reduce the memory size. The study is in fact the sinusoidal signal generation using direct digital synthesis (DDS) methods that store the sine signal samples and reduce the desired area (Sansaloni et al, 2007;De Caro and Strollo, 2005). For an N-point FFT, there are N/2 complex multipliers for being stored or calculated in run-time.…”

Section: Twiddle Read-only Memorymentioning

confidence: 99%

A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory

Kaya

Seke

2020

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Purpose This paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle. Design/methodology/approach A new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles. Findings With the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations. Originality/value This is an original paper, which has simultaneously in whole or in part been submitted anywhere else.

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Section: Twiddle Read-only Memorymentioning

confidence: 99%

A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory

Kaya

Seke

2020

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“…A multitude of researchers worked on twiddle factors to reduce the memory size required to hold them. The work is actually in parallel with the sinusoidal signal generation using direct digital synthesis (DDS) methods since storage area (for storing sine signal samples) reduction is desired in both [11,12]. For an N-point FFT there are N/2 complex multipliers that need either to be stored or calculated in run-time.…”

Section: Twiddle Rommentioning

confidence: 99%

Single Bank Dual-Port Memory-Based FFT for Field Programmable Gate Arrays

Seke¹,

Kaya²

2018

Anadolu University Journal of Science and Technology-a Applied Sciences and Engineering

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A new efficient memory-based FFT calculation method is presented using dual-port memories. Algorithm mainly targets Field Programmable Gate Arrays (FPGA). A semi-in-place calculation of FFT stages is presented to have both reads and writes in a single clock while keeping the memory size equal to the FFT size. The "semi-" word implies that the writes are not to the original/expected position. At each intermediate calculation, the outputs are written to the position where the reads are done so that the unused data is not overwritten. Compared to multi-bank memory FFT approaches, proposed memory addressing schema is both simpler to logically establish and requires lower count of logical elements. It is shown that the proposed approach accomplishes FFT task in lowest count of clock cycles among the single bank memory-based FFT algorithms. However, two-port single-bank size-N memory requirement limits the proposed design to radix-2.

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“…To minimize the actual storage of the FFT twiddle factors we utilize two optimizations. First, we use trigonometric properties to reduce the number of twiddle factors stored [11] from N/2 to N/8 + 1. For the 1024 point FFT this effectively reduces the number of twiddle factors stored from 512 to 129.…”

Section: Sar Algorithmmentioning

confidence: 99%

Design automation for a 3DIC FFT processor for synthetic aperture radar

Thorolfsson

Gonsalves

Franzon

2009

Proceedings of the 46th Annual Design Automation Conference

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This work discusses a 1024-point, memory-on-logic 3DIC FFT processor for synthetic aperture radar (SAR), sent to fabrication in the 180 nm MIT Lincoln Labs 3D FDSOI 1.5 V process[12] along with the design flow required to realize it with off-the-shelf commercial 2D tools. The work shows how the vertical dimension can be exploited for novel memory architecture tradeoffs that are not feasible in 2D, reducing the energy consumed per memory operation in the FFT by 60.3%. In comparison to its 2D counterpart, the SAR FFT processor exhibits a 53.0% decrease in average wire length, a 24.6% increase in maximum operating frequency and a 25.3% decrease in total silicon area.

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Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs

Cited by 7 publications

References 12 publications

A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory

A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory

Single Bank Dual-Port Memory-Based FFT for Field Programmable Gate Arrays

Design automation for a 3DIC FFT processor for synthetic aperture radar

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