A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory

Abstract

Purpose This paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle. Design/methodology/approach A new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles. Findings With the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations. Originality/value This is an original paper, which has simultaneously in whole or in part been submitted anywhere else.

Memory-Based Self-Ordering FFT for Efficient I/O Scheduling

“…It should be noted that aiming minimum memory (size 𝑁) gains importance when 𝑁 is large and posing problems in small FPGAs. However, it is possible to reduce memory down to 𝑁 with the efficient addressing algorithms [6,10,12].…”

Memory-Based FFT Architecture With Optimized Number of Multiplexers and Memory Usage

“…Researchers are trying to improve memory-based FFT architectures by suggesting new memory addressing schemes and decreasing resource requirements such as memory, chip area, etc. [6]- [10]. For an N -point FFT, some approaches use memories of size 2N or larger in order to avoid memory conflicts [12]- [15].…”

A 5.2-GS/s 8-Parallel 1024-Point MDC FFT

“…In order to satisfy the demands of 6G, efficient hardware architectures are required [4]- [15]. There are three main types of FFT hardware architectures: Memorybased [13], [14], fully parallel [15] and pipelined [4]- [10]. Memory-based FFT architectures consist of one or more processing elements and several banks of memory.…”