A Self-Calibrating Sub-Picosecond Resolution Digital-to-Time Converter

Nagaraj, G.; Miller, S.L.; Stengel, B.; Cafaro, Gio; Gradishar, T.; Olson, S.; Hekmann, R.

doi:10.1109/mwsym.2007.380397

Cited by 12 publications

(14 citation statements)

References 2 publications

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“…This fact reveals that, even with the combination of a multibit Sigma-Delta modulator and a DPWM, a higher order analog filter would be required. Alternative solutions have been proposed using Digital to Time converters (DTC) [5] to replace the counter of the DPWM modulator by a delay line implemented with digital delay cells. This way, N can be largely increased.…”

Section: Noise Shaped Pwm-dacmentioning

confidence: 99%

A time encoded decimation filter for noise shaped power DACs

Hernández

Fernández

Prefasi

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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This paper presents a new approach to reduce the out of band energy in a class D amplifier driven by a DAC. The proposed architecture is based on a Time Encoded Filter (TEF). The TEF operates as a discrete time linear system on the pulse widths of a PWM signal rather than on the amplitudes of a sequence. It only requires RC circuits, comparators and digital logic. Hence, it can be integrated along with the D/A converter. The main advantage of this approach is that the number of power inductors and capacitors of the off chip low pass filter may be reduced.

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Section: Noise Shaped Pwm-dacmentioning

confidence: 99%

A time encoded decimation filter for noise shaped power DACs

Hernández

Fernández

Prefasi

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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“…From a system perspective, such a conversion process should always be combined with an anti-imaging filter to eliminate the images that appear in the output spectrum. However, though DTCs are crucial in measurement instrumentation range finding and direct digital frequency synthesis [3]: their use is still relatively new. Moreover, their use with an anti-imaging filter is seldom seen in practice.…”

Section: Introductionmentioning

confidence: 99%

A low-cost ATE phase signal generation technique for test applications

Aouini

Chuai

Roberts

2010

2010 IEEE International Test Conference

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In this article, an accurate and low-cost clock delay generation system integrated in an automated test equipment (ATE) environment is presented. The input to this system is entirely digital and is driven by a single clock, which can be programmed from the ATE High Speed Digital (HSD) unit. Moreover, the digital input patterns can easily be generated in software off-line; hence, making this system ideal for automated test routines. The system is first discussed and characterized in Matlab under static and dynamic operating conditions. For the static behavior, the impact of the various design tradeoffs on the time resolution is investigated. With regards to the dynamic behavior, the linearity is assessed spectrally with a sinusoidal input and statistically using a Gaussian noise signal. A discrete prototype board is built to validate the correct operation of the system mounted on an A TE to function as a whole. With proper compensation and calibration, a delay resolution of 15 ps was achieved over an 8.4 ns range using a low-speed reference clock running at 16.67 MHz. It is shown through clock scaling that this resolution can improve in direct proportion to increases in the clock frequency.

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“…The DTC architecture [2] has several advantages of the traditional direct digital synthesis (DDS) architecture [3] such as, large frequency range, good frequency resolution and nearinstantaneous frequency transition. Unfortunately, the DDS architecture suffers from the disadvantage of high power consumption.…”

Section: Introductionmentioning

confidence: 99%

A low power 100 MHz – 2.5 GHz digital-to-time conversion based transmitter for constant-envelope direct digital modulation

Stengel

Talwalkar

Gradishar

et al. 2009

2009 IEEE Radio Frequency Integrated Circuits Symposium

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This paper reports a flexible direct digital modulation based low power transmitter in 90 nm CMOS that supports constant-envelope modulation using phase or frequency modulation for carrier frequencies from 100 MHz to 2.5 GHz. For rectangular filtered 8-PSK modulation from 1 K symbol/s to 20 M symbol/s the RMS phase error is less than 4 deg. Frequency modulation is measured via filtered frequency shift keying (FSK) schemes used in two common standard protocols, GSM and APCO-25. GSM phase error at 800-900 MHz as well as 1900 MHz is less than 1 deg RMS. APCO-25 FSK error is less than 2% across bands from VHF (~130 MHz) to UHF (~400 MHz) to 800 MHz. Measured adjacent channel power ratio (ACPR) are within specification.The synthesizer power drain is 130 mW with an active area of 0.7 mm 2 .

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A Self-Calibrating Sub-Picosecond Resolution Digital-to-Time Converter

Cited by 12 publications

References 2 publications

A time encoded decimation filter for noise shaped power DACs

A time encoded decimation filter for noise shaped power DACs

A low-cost ATE phase signal generation technique for test applications

A low power 100 MHz – 2.5 GHz digital-to-time conversion based transmitter for constant-envelope direct digital modulation

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A Self-Calibrating Sub-Picosecond Resolution Digital-to-Time Converter

Cited by 12 publications

References 2 publications

A time encoded decimation filter for noise shaped power DACs

A time encoded decimation filter for noise shaped power DACs

A low-cost ATE phase signal generation technique for test applications

A low power 100 MHz &#x2013; 2.5 GHz digital-to-time conversion based transmitter for constant-envelope direct digital modulation

Contact Info

Product

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A low power 100 MHz – 2.5 GHz digital-to-time conversion based transmitter for constant-envelope direct digital modulation