A low-cost ATE phase signal generation technique for test applications

Aouini, Sadok; Chuai, Kun; Roberts, G.W.

doi:10.1109/test.2010.5699202

Cited by 14 publications

(15 citation statements)

References 7 publications

(17 reference statements)

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“…The timing of the edge T Data is produced through a phase-modulating encoding process performed in software using a ΣΔ modulator and a digital-to-time converter (DTC), followed by storage in a 1-bit circular memory. The output of this memory is then passed to a time-mode filter (TMF) realized using either a PLL [4], a DLL [6] or time-mode SC reconstruction filter [1] -more on this in a moment. In a similar vein, both the level crossing of a sampling process and timing edge denoted by parameters V TH and T STRB are realized using the bottom two sets of sub-blocks in channels 3 and 4.…”

Section: System Overviewmentioning

confidence: 99%

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

Bielby

Chowdhury

et al. 2016

J Electron Test

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An instrument for on-chip measurement of transceiver transmission capability is described that is fully realizable in CMOS technology and embeddable within an SoC. The instrument can be used to inject and extract the timing and voltage information associated with signals in high-speed transceiver circuits that are commonly found in data communication applications. At the core of this work is the use of ΣΔ amplitude-and phase-encoding techniques to generate both the voltage and timing (phase) references, or strobes used for high-speed sampling. The same technique is also used for generating the test stimulant for the device-under-test.cloud computing, etc. In order to keep component costs down, low-cost test techniques are essential. One strategy is to incorporate test circuits directly on-chip to standardize test equipment access, improve accuracy and repeatability, and to contribute to short test times through parallel test procedures. In some cases, an on-chip instrument may be the only means to capture information associated with some internal core circuit. An important attribute of such on-chip test circuits is a low silicon area overhead. In addition, such on-chip instruments are not bandwidth limited by the test channel, so tests can be performed at the desired operating frequencies and speeds [7]. A software programmable, probabilistic test instrument using ΣΔ-encoded phase/amplitude-signal generators is to be described in this paper.This work in a shorter form was first presented at the 20th International Mixed-Signal Testing Workshop [14]. In that publication the general concept of the probabilistic instrument was proposed and demonstrated with discrete components. In this publication, our first attempt at integrating the concept into a 130 nm CMOS IC realization. The results of this endeavor will also be described here. While our intent is to use this instrument as part of an embedded instrument for high-speed transceivers, however, at this point in time, the IC results do not operate anywhere close to the 1 Gbps rates required by today's I/Os. This is not meant to be a definitive statement that the approach is not sound but rather the results gather here is a testament of the working principle. It is expected that future work will improve the operating speed and measurement resolution suitable for next generation transceiver ICs. This paper will begin with a system overview of the probabilistic test instrument (PTI) in Section II, including a description of various methods for phase and voltage signal generation using sigma-delta encoding methods, and CDF extraction. Section III will describe the critical decision-making circuits such as the D-type flip-flops and comparator circuits used in the CMOS IC implementation. Section IV will describe the Responsible Editors:

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Section: System Overviewmentioning

confidence: 99%

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

Bielby

Chowdhury

et al. 2016

J Electron Test

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“…Once encoded by the DTC, every output '0' value from the sigma-delta modulator is mapped to a '0110' bit sequence and every' I' is mapped to a '11 00' bit sequence. In this paper, both the sigma-delta modulator and the DTC are implemented in software [6]. The phase-encoded bit-sequences are first generated in software that models the modulator and DTC, and are then loaded into the circular memory bank through the use of a multiplexer.…”

Section: Sigma-delta Bit Stream Generationmentioning

confidence: 99%

Sub-gate-delay edge-control of a clock signal using DLLs and ΣΔ modulation techniques

Bielby

Roberts

2014

2014 IEEE 27th Canadian Conference on Electrical and Computer Engineering (CCECE)

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Many high-speed communication applications require precise edge-control for establishing ideal sampling conditions. A delay-locked loop (DLL) is often used to phase shift the incoming reference clock signal in increments of the propagation delay of a single inverter circuit.Through the application of sigma-delta modulation techniques, this paper will demonstrate how a DLL can be used to provide precise edge control with sub-gate-delay resolution.

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“…A digital input can be converted to a phase modulated signal through a digital-to-time conversion process as described in [1]. Referring to Fig.…”

Section: Phase Encodingmentioning

confidence: 99%

“…A top-down design methodology was employed to impose a desired phase transfer function, as described in [1]. The IBM cmrf8sf 130 nm process was chosen as the technology for fabrication.…”

Section: Custom Pll Designmentioning

confidence: 99%

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High Speed On-Chip Signal Generation for Debug and Diagnosis

2012

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This article presents methods and circuits for synthesizing test signals in the time/frequency domain. An arbitrary signal is first encoded using sigma-delta modulation in the digital amplitude-domain and converted to the time or frequency domain through a digital-to-time converter (DTC) or digital-to-frequency converter (DFC) operation realized in software. In hardware, the resulting bit-stream is inputted cyclically to a high-order phase-locked loop (PLL) behaving as a time-mode reconstruction filter in the appropriate domain (time or frequency). A high-speed prototype implementation consisting of a 4th order PLL built in 0.13 μm complementary metal oxide semiconductor (CMOS) process with an off-chip loop filter has been fabricated and used to generate signals at 4 GHz. The digital nature and portability of the phase/ frequency test signal generation process makes the proposed scheme compatible with the IEEE 1149.1 test bus standard and easily amenable to any testing environment: production, characterization, design-fortest (DFT), or built-in self-test (BIST).

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A low-cost ATE phase signal generation technique for test applications

Cited by 14 publications

References 7 publications

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

Sub-gate-delay edge-control of a clock signal using DLLs and ΣΔ modulation techniques

High Speed On-Chip Signal Generation for Debug and Diagnosis

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A low-cost ATE phase signal generation technique for test applications

Cited by 14 publications

References 7 publications

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

Sub-gate-delay edge-control of a clock signal using DLLs and &#x03A3;&#x0394; modulation techniques

High Speed On-Chip Signal Generation for Debug and Diagnosis

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Sub-gate-delay edge-control of a clock signal using DLLs and ΣΔ modulation techniques