A self-aligned gate III-V heterostructure FET process for ultrahigh-speed digital and mixed analog/digital LSI/VLSI circuits

Akinwande, A.I.; Ruden, P.P.; Vold, P.J.; Han, C. J.; Grider, David; Narum, D. H.; Nohava, Thomas; Nohava, J.C.; Arch, D.K.

doi:10.1109/16.40901

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

Contact Info

customersupport@researchsolutions.com

10624 S. Eastern Ave., Ste. A-614

Henderson, NV 89052, USA

Blog Terms and Conditions API Terms Privacy Policy Contact Cookie Preferences Do Not Sell or Share My Personal Information

Made with 💙 for researchers

Part of the Research Solutions Family.

A self-aligned gate III-V heterostructure FET process for ultrahigh-speed digital and mixed analog/digital LSI/VLSI circuits

Cited by 7 publications

References 23 publications

Photoluminescence characterization of the effects of rapid thermal annealing on AlGaAs/GaAs modulation-doped quantum wells

Photoluminescence characterization of the effects of rapid thermal annealing on AlGaAs/GaAs modulation-doped quantum wells

AlGaAs/InGaAs/GaAs quantum well doped channel heterostructure field effect transistors

Heterostructure FET model including gate leakage

Contact Info

Product

Resources

About