A self-adaptive system architecture to address transistor aging

Khan,; Kundu,

doi:10.1109/date.2009.5090637

Cited by 39 publications

(19 citation statements)

References 17 publications

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“…6, we assumed that the frequencies of CLK1 (fclk1) and CLK2 (fclk2) are respectively 1 GHz and 500 MHz which are synchronized. We also assumed that the target circuit uses the frequency guard-band of 20% [5]. This means that originally the clock domain 1 and 2 are able to respectively operate at 1.2 GHz and 600 MHz which are maximum clock frequencies.…”

Section: Resultsmentioning

confidence: 99%

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An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

Yi¹

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-onchip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.

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Section: Resultsmentioning

confidence: 99%

“…The guard-band interval, as shown in Fig. 1, is the timing guard-band given to account for expected performance loss over device life time [5,6].…”

Section: Introductionmentioning

confidence: 99%

An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

Yi¹

2013

JSTS:Journal of Semiconductor Technology and Science

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“…However, their method is not applicable to SoCs or ASICs, and it cannot measure the amount of degradation. Khan, et al [9] proposed a method that is more tightly connected to the OS. Functional test that measures F max or V min is applied at checkpoints that OS controls.…”

Section: Introductionmentioning

confidence: 99%

“…Another approach [8][9] is an on-line testing during test mode, which is conducted by an operating system (OS). Li, et al [8] applied their method for a multi-core processor.…”

Section: Introductionmentioning

confidence: 99%

A circuit failure prediction mechanism (DART) for high field reliability

Suzuki

Kajihara

Miura

et al. 2009

2009 IEEE 8th International Conference on ASIC

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This paper presents a novel circuit failure prediction mechanism for high field reliability. On-line testing at a power-on/off time of a system detects the circuits' delay degradation that is caused by aging. Dedicated test vectors are applied using BIST architecture.Embedded ring oscillators are utilized to compensate the measured delay values for temperature or voltage shift. The concept and necessary conditions for the mechanism are introduced and some preliminary experimental results show the possible effectiveness ofthe approach.

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“…Periodic self-test is a complementary technique that enables the detection of aging-induced defects 1 [16] [18] [29]. Concurrent self-test enables a component [28] or a system [12] to test itself concurrently with its normal operation.…”

Section: Introductionmentioning

confidence: 99%

Error prediction based on concurrent self-test and reduced slack time

Gherman

Massas

Evain

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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Small circuit defects occurred during manufacturing and/or enhanced/induced by various aging mechanisms represent a serious challenge in advanced scaled CMOS technologies. These defects initially manifest as small delay faults that may evolve in time and exceed the slack time in the clock cycle period. Periodic tests performed with reduced slack time provide a low-cost solution that allows to predict failures induced by slowly evolving delay faults. Unfortunately, such tests have limited fault coverage and fault detection latency.Here, we introduce a way to complement or completely replace the periodic testing with reduced slack time. Delay control structures are proposed to enable arbitrarily small parts of the monitored component to switch fast between a normal operating mode and a degraded mode characterized by a smaller slack time. Only two or three additional transistors are needed for each flip-flop in the monitored logic. Micro-architectural support for a concurrent selftest of pipelined logic that takes benefit of the introduced degraded mode is presented as well. Test stimuli are produced on the fly by the last two valid operations executed before each stall cycle. Test result evaluation is facilitated by the replication of the last valid operation during a stall cycle. Protection against transient faults can be achieved if each operation is replicated via stall cycle insertion.

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A self-adaptive system architecture to address transistor aging

Cited by 39 publications

References 17 publications

An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

A circuit failure prediction mechanism (DART) for high field reliability

Error prediction based on concurrent self-test and reduced slack time

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