A circuit failure prediction mechanism (DART) for high field reliability

Suzuki, Yasuo; Kajihara, Seiji; Miura, Yoshio; Yoneda, Tomokazu; Ohtake, Satoshi; Inoue, Michiko; Fujiwara, Hideo

doi:10.1109/asicon.2009.5351352

Cited by 27 publications

(11 citation statements)

References 13 publications

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“…TDDB, in which continuous stresses to a gate oxide-film causes the insulating film breakdown, results in slow delay degradation up to a certain point and causes a sudden delay increase or a failure as shown in Fig. 1 [6]. However, delay variations are caused not only by aging mechanisms but also by variations of environmental conditions such as voltage and temperature.…”

Section: Introductionmentioning

confidence: 95%

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A Failure Prediction Strategy for Transistor Aging

Yoneda

Inoue

et al. 2012

IEEE Trans. VLSI Syst.

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This paper presents a novel failure prediction technique that is applicable for system-on-chips (SoCs). Highly reliable systems such as automobiles, aircrafts, or medical equipments would not allow any interruptive erroneous responses during system operations, which might result in catastrophes. Therefore, we propose a failure prediction technique that can be applied during an idle time when a system is not working, such as power-on/-off time. To achieve high reliability in the field, the proposed technique should take into consideration various types of aging mechanisms and the testing environment of voltage and temperature which is uncontrollable in the field. Therefore, we propose: 1) an accurate delay measurement technique considering the variation due to voltage and temperature and 2) an adaptive test scheduling that gives more test chances to more probable degrading parts. Experimental results show the required memory space and area cost for implementing the proposed technique.

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Section: Introductionmentioning

confidence: 95%

“…However, delay variations are caused not only by aging mechanisms but also by variations of environmental conditions such as voltage and temperature. Accordingly, profiling voltage and temperature is needed for accurate delay measurement [6].…”

Section: Introductionmentioning

confidence: 99%

A Failure Prediction Strategy for Transistor Aging

Yoneda

Inoue

et al. 2012

IEEE Trans. VLSI Syst.

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“…In known approaches to wear-out monitoring [9], [10], [16], [11], [12], [13], [14], some consider electromigration [9], some consider NBTI (Negative Bias Temperature Instability) [11], [12], [14], some gate oxide breakdown [9], [13] or some other or unspecified wear-out mechanism [16], [17]. Several of the known wear-out mechanisms have in common that they affect the signal propagation delay through a circuit.…”

Section: Previous Work On Electromigration Wear-out Monitoringmentioning

confidence: 99%

Measurement point selection for in-operation wear-out monitoring

Ingelsson

Chang

Larsson

2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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-In recent IC designs, the risk of early failure due to electromigration wear-out has increased due to reduced feature dimensions. To give a warning of impending failure, wearout monitoring approaches have included delay measurement circuitry on-chip. Due to the high cost of delay measurement circuitry this paper presents a method to reduce the number of necessary measurement points. The proposed method is based on identification of wear-out sensitive interconnects and selects a small number of measurement points that can be used to observe the state of all the wear-out sensitive interconnects. The method is demonstrated on ISCAS85 benchmark ICs with encouraging results.

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“…Y. Sato et al [6] presented a circuit failure prediction mechanism named DART which stands for Degrade factor, Accuracy, Report, and Test Coverage. They also use pre-stored test patterns and refer to the measured voltage and temperature, which are uncontrollable in field but affect delay variation, to improve the delay measurement accuracy.…”

Section: Related Workmentioning

confidence: 99%

“…In applications requiring high field reliability such as medical equipment, satellites, aircrafts, and power plants, performance degradation and a failure can trigger life-threatening disasters. In order to prevent a disaster, aging monitoring techniques have been presented [5][6][7][8][9][10][11][12]. They give a warning to the system user or conduct self-repair before a failure occurs.…”

Section: Introductionmentioning

confidence: 99%

A Scan-Based On-Line Aging Monitoring Scheme

Yoneda

Inoue

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. This paper presents a scan-based on-line aging monitoring scheme which monitors aging during normal operation and gives an alarm if aging is detected so that the system users take action before a failure occurs. We illustrate our modified scan chain architecture and aging monitoring control method. Experimental results show our simulation results to verify the functions of the proposed scheme.

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A circuit failure prediction mechanism (DART) for high field reliability

Cited by 27 publications

References 13 publications

A Failure Prediction Strategy for Transistor Aging

A Failure Prediction Strategy for Transistor Aging

Measurement point selection for in-operation wear-out monitoring

A Scan-Based On-Line Aging Monitoring Scheme

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