A Scalable Multilevel Metallization with Pillar Interconnections and Interlevel Dielectric Planarization

Abstract

A multilevel metallization system, which results in smooth topography and high packing density by overcoming many of the limitations of the conventional approach, has been developed. In this scheme metallic pillars are used for interlevel wiring, instead of traditional contacts and vias. Refractory metal layers are employed at all levels as an etch stop/ diffusion barrier with a self-aligned metal silicide used to insure low contact resistance between conductor (aluminum) and silicon substrate. Planarized SiO2 is used as the dielectric at each level in which planarization of the dielehtric and exposure of the underlying metallization are achieved by the etchback technique using sacrificial photoresist films. This interconnection scheme can be extended to any number of levels of interconnection and may be readily scaled for use in submicron ULSI technologies.

The planar anodic Al 2 O 3 -ZrO 2 nanocomposite capacitor dielectrics for advanced passive device integration

“…IPDs are generally produced using standard microfabrication technologies: physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), wet and dry chemical or plasma-chemical etching, and lithographic techniques [ 2 , 3 , 11 ]. Notably, these approaches require more complex efforts to planarize the layers and blend them in multilayer stacks [ 12 , 13 ].…”