A Scalable FPGA-based Multiprocessor

Abstract

It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive large-scale computing applications, such as molecular dynamics simulations of biological systems, underscore the need for even greater speedups to address relevant length and time scales.In this work, we propose an architecture for a scalable computing machine built entirely using FPGA computing nodes. The machine enables designers to implement largescale computing applications using a heterogeneous combination of hardware accelerators and embedded microprocessors spread across many FPGAs, all interconnected by a flexible communication network. Parallelism at multiple levels of granularity within an application can be exploited to obtain the maximum computational throughput. By focusing on applications that exhibit a high computation-tocommunication ratio, we narrow the extent of this investigation to the development of a suitable communication infrastructure for our machine, as well as an appropriate programming model and design flow for implementing applications.By providing a simple, abstracted communication interface with the objective of being able to scale to thousands of FPGA nodes, the proposed architecture appears to the programmer as a unified, extensible FPGA fabric. A programming model based on the MPI message-passing standard is also presented as a means for partitioning an application into independent computing tasks that can be implemented on our architecture. Finally, we demonstrate the first use of our design flow by developing a simple molecular dynamics simulation application for the proposed machine, which runs on a small platform of development boards.

Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI

“…First, let us specify the scope of the paper by categorizing the types of high-performance machines; this categorization was first introduced in Patel [16]. As previously stated, FPGAs are now an active field of research in the HPC world, and based on the trend to incorporate FPGAs in computation, high-performance machines are classified into three categories.…”

“…Although Class 3 machines are application-specific in nature, reconfigurability is implicit in the FPGAs and they can be reconfigured as needed. Examples of Class 3 machines are BEE [3], TMD [16], and the one presented in Charles [2]. In this paper, we focus on Class 3 machines.…”

A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPI

“…TMD-MPI has been developed as a result of the need for a programming model for the TMD machine being developed at the University of Toronto [10]. The TMD machine is a scalable Multi-FPGA configurable system designed to accelerate computing intensive applications.…”

A profiler for a heterogeneous multi-core multi-FPGA system

“…This thesis focus is a profiler for the TMD [4] [5] [6], a heterogeneous multi-core multi-FPGA system designed at the University of Toronto that uses the message passing paradigm for communications. The main purpose of this profiler is to give insight into the communications occurring between nodes and the computation performed by each node.…”