A Scalable 2.4-to-2.7GHz Wi-Fi/WiMAX Discrete-Time Receiver in 65nm CMOS

Montaudon, F.; Mina, Rayan; Tual, Stephane Le; Joet, Loic; Saias, D.; Hossain, R.; Sibille, Florent; Corre, Christian; Carrat, V.; Chataigner, E.; Lajoinie, J.; Dedieu, S.; Paillardet, F.; Perea, E.

doi:10.1109/isscc.2008.4523207

Cited by 13 publications

(27 citation statements)

References 6 publications

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“…5), taking an active area=0.5mm 2 . The chip is measured on PCB and the input port has R src =50Ohm for all tests.…”

Section: Resultsmentioning

confidence: 99%

“…Sampling early at RF allows more discretetime and digital signal processing, which can have advantages with respect to the compatibility with digital CMOS technology [1] [2] and SoC integration [3]. However, most published RF-sampling receivers are narrowband, and compared to RF-mixing receivers, a number of extra challenges exist to apply RF-sampling to wideband software-defined radio (SDR) receivers [4].…”

Section: Introductionmentioning

confidence: 99%

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A tunable 300–800MHz RF-sampling receiver achieving 60dB harmonic rejection and 0.8dB minimum NF in 65nm CMOS

Klumperink

Saavedra

et al. 2009

2009 IEEE Radio Frequency Integrated Circuits Symposium

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-A 300-800MHz CMOS radio receiver aiming at software-defined radio is proposed. It exploits an LNA preceded by a tunable LC filter with one external coil to achieve voltage amplification for low NF and low-pass filtering to improve the 3 rd and 5 th harmonic rejection of an RF-sampling receiver to >60dB. The balun-LNA provides partial IM3 compensation, to drive a wideband sampling downconverter. The measured gain is 22-28dB while NF ranges from 0.8-4.3dB. The core consumes 6mW and clock takes 12mW.

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“…5), taking an active area=0.5mm 2 . The chip is measured on PCB and the input port has R src =50Ohm for all tests.…”

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A tunable 300–800MHz RF-sampling receiver achieving 60dB harmonic rejection and 0.8dB minimum NF in 65nm CMOS

Klumperink

Saavedra

et al. 2009

2009 IEEE Radio Frequency Integrated Circuits Symposium

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“…It is based on [4], where the charge sampling receiver was developed for the WiFi/WiMAX standard. Figure 5.a.…”

Section: Lo Iqmentioning

confidence: 99%

A digital Cartesian feedback path design for 2.4GHz ISM band standards

Zeleny¹,

Wurm²,

Vincent³

2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

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A digital radiofrequency (RF) transmitter (TX) architecture for software defined radio (SDR) is proposed in this paper. Nowadays the tendency is to integrate many telecommunication standards within a unique circuit. This leads to consider reconfigurable transmission architectures which contain a minimum of analogue components. To address the non linearity issue posed by the power amplifier (PA), an adaptive baseband digital predistortion mechanism was favored for its stability and software reconfigurability. The subsequent predistortion algorithm collects the data from the PA trough a dedicated feedback path. In the State-of-the-Art proposed feedback paths are not reconfigurable. Either they contain analogue filters. In proposed feedback path, the filtering is performed by charge sampling at the entrance of analog-todigital converter (ADC). We present the analysis and model of the proposed feedback path. The scaling of ADC resolution and bandwidth for the most stringent standard in ISM 2.4 GHz band is reported.

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“…The maximum input frequency of the sampler is 5.8GHz. A subsampling stage at 600 Ms/s has also been used in [4] to down-convert the WiFi signals at 2.4GHz. Meanwhile, this architecture is not suitable for direct subsampling of signal at 60GHz because of very stringent constraints on bandwidth, folded noise and clock jitter.…”

Section: Introductionmentioning

confidence: 99%

A reconfigurable 60GHz subsampling receiver architecture with embedded channel filtering

Grave

Frappé

2012

2012 IEEE International Symposium on Circuits and Systems

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This paper presents a 60GHz heterodyne receiver architecture with IF sub-sampling. A particular arrangement of the frequency plan allows anti-alias filtering by the chargedomain subsampler. Down-conversion, channel filtering and IQ demodulation are merged into a unique operator without any extra cost in terms of area and power consumption. The proposed architecture is able to receive up to 4 bonded channels and complies with the requirements of the standards for 60GHz wireless communications. The result of this study shows that subsampling is a good candidate for low power and configurable receivers for mmW wireless communications.I.

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A Scalable 2.4-to-2.7GHz Wi-Fi/WiMAX Discrete-Time Receiver in 65nm CMOS

Cited by 13 publications

References 6 publications

A tunable 300–800MHz RF-sampling receiver achieving 60dB harmonic rejection and 0.8dB minimum NF in 65nm CMOS

A tunable 300–800MHz RF-sampling receiver achieving 60dB harmonic rejection and 0.8dB minimum NF in 65nm CMOS

A digital Cartesian feedback path design for 2.4GHz ISM band standards

A reconfigurable 60GHz subsampling receiver architecture with embedded channel filtering

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A Scalable 2.4-to-2.7GHz Wi-Fi/WiMAX Discrete-Time Receiver in 65nm CMOS

Cited by 13 publications

References 6 publications

A tunable 300&#x2013;800MHz RF-sampling receiver achieving 60dB harmonic rejection and 0.8dB minimum NF in 65nm CMOS

A tunable 300&#x2013;800MHz RF-sampling receiver achieving 60dB harmonic rejection and 0.8dB minimum NF in 65nm CMOS

A digital Cartesian feedback path design for 2.4GHz ISM band standards

A reconfigurable 60GHz subsampling receiver architecture with embedded channel filtering

Contact Info

Product

Resources

About

A tunable 300–800MHz RF-sampling receiver achieving 60dB harmonic rejection and 0.8dB minimum NF in 65nm CMOS

A tunable 300–800MHz RF-sampling receiver achieving 60dB harmonic rejection and 0.8dB minimum NF in 65nm CMOS