A ring architecture strategy for BIST test pattern generation

Fagot, C.; Gascuel, Olivier; Girard, Patrick; Landrault, C.

doi:10.1109/ats.1998.741650

Cited by 15 publications

(13 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The test application time is compared with related BIST solutions without storage memories, as shown in the table, they contains paper [2], paper [9], paper [11] and paper [16]. The last column is the test application time and the hardware cost of ours where the hardware cost is measured by the number of gate they contain.…”

Section: Resultsmentioning

confidence: 99%

“…However, because complex circuits often contains some hard-to-detect faults that random-pattern resistant, the conventional BIST often requires long test application time, and hard to achieve high fault coverage [1] .To solve these problems, many of techniques have been proposed. Test point insertion [2][3][4] , weighted pattern testing [5][6][7][8] , and reseeding [9][10][11] are three most popular logic BIST schemes.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A new BIST scheme with encoding logic to achieve complete fault coverage

Zhang

Mei

Wang

et al. 2015

Future Energy, Environment and Materials II

View full text Add to dashboard Cite

Abstract-Built-in Self Test(BIST)has been proved as one of the effective design for testability techniques, where on-chip test architectures are designed to test the digital circuits themselves. To reduce test application time and improve fault coverage, A deterministic Built-in Self Test(BIST) technique that can get complete fault coverage without using any storage device is proposed in this paper. The test architecture contains a novel on chip encoding logic that generates all required test vectors in real time. Experimental results show that the proposed technique requires much less test application time to achieve complete fault coverage for all testable stuck-at faults with reasonable hardware cost.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A new BIST scheme with encoding logic to achieve complete fault coverage

Zhang

Mei

Wang

et al. 2015

Future Energy, Environment and Materials II

View full text Add to dashboard Cite

show abstract

“…Examples include the following: the design for testability technique [5,6] in which observation points are inserted in CUT and the number of rpr faults is reduced [7], the bit-fixed technique [8] in which specific logic values are fixed at reliable bit positions, the technique in which the initial values of counters are reseeded [9], and the TPG for BIST utilizing vector obtained by ATPG (hereafter called ATPG vectors) [10]. A technique for core-based LSIs has also been proposed [1].…”

Section: Introductionmentioning

confidence: 99%

BIST‐oriented test pattern generator for detection of transition faults

Asakawa

Iwasaki

Kajihara

2003

Systems & Computers in Japan

View full text Add to dashboard Cite

SUMMARYAs a technique for complementing the long testing time, which is a shortcoming of pseudo-random pattern test, we will propose a BIST-oriented test pattern generator (TPG) which achieves high fault detection efficiency with a short testing time for transition faults. The proposed TPG is composed by adding LFSR, shift registers, and multiplexers to the scan part. The partial sequences of ATPG vectors are stored in an on-chip RDM or external tester and the scan-in is performed. The test patterns are generated, which are the result of mixing the partial sequence of ATPG vectors and the pseudo-random vectors generated by LFSR. Since the random pattern resistant faults will be detected by the partial sequences of ATPG vectors, a high fault detection efficiency can be achieved with a short testing time. Since it is not necessary to perform the scan-in for every operation clock, the real operation speed test using a low-speed tester is possible. We will also show a technique for reducing the ATPG vectors to be stored. The proposed technique is evaluated, by using ISCAS benchmark circuits, for testing time, fault detection efficiency, and hardware quantity, and the effectiveness of the proposed technique is examined.

show abstract

“…One possible way to do this is to select the "seed" very carefully. Several procedures to select seeds have already been studied [16][17][18][19][20][21]. Bayraktaroglu et al examined the PRPG structure and selection approaches [16].…”

Section: Introductionmentioning

confidence: 99%

“…Lempel et al proposed an LFSR seed-selecting algorithm that used the theory of discrete logarithms [17]. The technique Fagot et al used [18] estimates test quality by using the Hamming distance between the testcube and the test pattern that is output from the LFSR for a bit-flipping BIST. In Fagot et al's later study [19], fault simulation computes an efficient LFSR seed which outputs the test sequence including a testcube.…”

Section: Introductionmentioning

confidence: 99%