A new BIST scheme with encoding logic to achieve complete fault coverage

Abstract

Abstract-Built-in Self Test(BIST)has been proved as one of the effective design for testability techniques, where on-chip test architectures are designed to test the digital circuits themselves. To reduce test application time and improve fault coverage, A deterministic Built-in Self Test(BIST) technique that can get complete fault coverage without using any storage device is proposed in this paper. The test architecture contains a novel on chip encoding logic that generates all required test vectors in real time. Experimental results show that the proposed technique requires much less test application time to achieve complete fault coverage for all testable stuck-at faults with reasonable hardware cost.