A rigorous surface-potential-based I-V model for undoped cylindrical nanowire MOSFETs

Lin, Shang-Wei; Zhou, Xing; See, Guan Huei; Zhu, Zhengming; Lim, Gerard Joseph; Wei, Chengqing; Zhu, Guojun; Yao, Zhaolin; Wang, X.F.; Yee, M.; Zhao, Long; Hou, Zhufeng; Ang, L. K.; Lee, T.S.; Chandra, William

doi:10.1109/nano.2007.4601326

Cited by 13 publications

(22 citation statements)

References 7 publications

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“…which are similar to the PB equations (in [45] and [46], respectively) for undoped body under the unipolar assumption, for which p 0 = n i and φ F = 0. Based on the general solutions in [45] and [46] for s-DG and GAA, respectively, the φ o solutions for (61a) and (61b) can be found as [8] φ o,c = v th ln B ss,c A ss,c − 2v th ln cos arccos…”

Section: Unification Of Soi/dg/gaa Modelssupporting

confidence: 62%

“…However, due to its unique feature of V c -independence below V t , together with the effective drain-source voltage in the I ds model [see (46) below], it does not require very accurate φ s solutions, contrary to those iterative/explicit φ s -based models. Although the single-piece φ seff (27) is available, it is not directly used in the charge modeling; instead, the unified regional solutions (φ acc , φ ds ) are used in the URM for terminal charges.…”

Section: Xsim: Unification Of Mos Compact Modelsmentioning

confidence: 99%

“…General solutions for DG/GAA MOSFETs have been studied [43][44][45][46], and most literatures are based on undoped body and one type of carrier (unipolar). Rigorous iterative φ s solution in undoped s-DG with two carriers (bipolar) has been obtained [47], which shows only a ∼nV error in φ s and a singularity in dC gg /dV g at flatband due to the unipolar assumption.…”

Section: Unification Of Soi/dg/gaa Modelsmentioning

confidence: 99%

“…Based on the general solutions in [45] and [46] for s-DG and GAA, respectively, the φ o solutions for (61a) and (61b) can be found as [8] φ o,c = v th ln B ss,c A ss,c − 2v th ln cos arccos…”

Section: Unification Of Soi/dg/gaa Modelsmentioning

confidence: 99%

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Unification of MOS compact models with the unified regional modeling approach

Zhou

Zhu²,

See

et al. 2011

J Comput Electron

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This paper reviews the development of the MOS-FET model (Xsim), for unification of various types of MOS devices, such as bulk, partially/fully-depleted SOI, doublegate (DG) FinFETs and gate-all-around (GAA) siliconnanowires (SiNWs), based on the unified regional modeling (URM) approach. The complete scaling of body doping and thickness with seamless transitions from one structure to another is achieved with the unified regional surface potential, in which other effects (such as those due to poly-gate doping and quantum-mechanical) can be incorporated. The unique features of the Xsim model and the essence of the URM approach are described.

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Section: Unification Of Soi/dg/gaa Modelssupporting

confidence: 62%

Section: Xsim: Unification Of Mos Compact Modelsmentioning

confidence: 99%

Section: Unification Of Soi/dg/gaa Modelsmentioning

confidence: 99%

Section: Unification Of Soi/dg/gaa Modelsmentioning

confidence: 99%

See 2 more Smart Citations

Unification of MOS compact models with the unified regional modeling approach

Zhou

Zhu²,

See

et al. 2011

J Comput Electron

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“…However, [32] describes a PSP-based compact model for FinFETs which, taking advantage of the similarities of its hierarchical structure with PSP model, is particularly suitable for circuit simulations. Compact models for Gate-All-Around (GAA) MOSFETs, reported in [33] and [34], present expressions for charge and current including fitting parameters to increase accuracy. The study of short-channel effects in GAA MOSFETs in [35] lead to analytical expressions for threshold voltage, subthreshold swing and channel length modulation.…”

Section: B Multi-gate Device Modelsmentioning

confidence: 99%

Computationally Efficient Multiple-Independent-Gate Device Model

Antidormi

Frache

Graziano

et al. 2016

IEEE Trans. Nanotechnology

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Abstract-Nanowire Field Effect Transistors (FETs) with multiple independent gates around a silicon channel feature ultimate gate control and are regarded as promising candidates for next generation transistors. Being inherently more complex than conventional gate-all-around nanowire FETs, they require longer simulation times, especially with numerical simulations. We present a new model enabling the efficient computation of voltages and current in modular semiconductor structures with an arbitrary number of independent gate regions. Its validity extends on Gate-All-Around MOSFETs, FinFETs and gate-less channels. It exploits existing models for conventional devices and builds results on top of these. Being completely general, the method is independent from the models used to describe each region, a charge-based model in our case. Applied to a multiindependent-gate nanowire FET structure, extensive comparison of the proposed method with results from physics-based TCAD Atlas software and with numerical exact results show very good agreement with relative errors of less than 1.8% for potentials and less than 4% for currents, under a broad variations of physical parameters as well as biasing conditions. Interpreted language implementation shows a performance advantage in excess of one order of magnitude with respect to standard optimized numerical methods, still providing excellent accuracy, and making it suitable for implementation in circuit simulators.

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Parameteric optimization of SiGe S/D NT JLFET using analytical modeling to improve L‐BTBT induced GIDL

Thakur,

Dhiman,

Wadhwa

et al. 2024

Int J Numerical Modelling

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In the present work, we investigate the impact of structure dimensional parameters on the short channel effects which occurs especially below 20 nm regime particularly gate induced drain leakage (GIDL) current. Using technology computer aided design simulation (TCAD), we have examined the GIDL for SiGe as source/drain in NTJLFET. The structural dimensional parameters such as the nanotube thickness, core and outer gates thickness and gate electrode work function shows the significant impact on the band to band tunneling in lateral direction (L‐BTBT) which induced GIDL current. It is analyzed that increase in the nanotube thickness and physical oxide thickness increase the GIDL current, while increasing the gate electrode work function, core gate and outer gate thicknesses gives reduced GIDL current. The SiGe S/D NTJLFET produce a remarkable high ION/IOFF ratio ~ 1011. A compact model for GIDL current is also developed which shows the dependency of structure parameters on leakage current. The SiGe has been incorporated as source and drain in NTJLFET which creates the energy band discontinuity. Furthermore, SiGe S/D NTJLFET is fairly compared with the conventional NT JLFET and nanowire (NW) JLFET and shows an improved performance.

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A rigorous surface-potential-based I-V model for undoped cylindrical nanowire MOSFETs

Cited by 13 publications

References 7 publications

Unification of MOS compact models with the unified regional modeling approach

Unification of MOS compact models with the unified regional modeling approach

Computationally Efficient Multiple-Independent-Gate Device Model

Parameteric optimization of SiGe S/D NT JLFET using analytical modeling to improve L‐BTBT induced GIDL

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