A RESURF P-N bimodal LDMOS suitable for high voltage power switching applications

Zhang, Yongxi; Pendharkar, S.; Hower, P.L.; Giombanco, Salvatore; Amoroso, A.; Marino, F.

doi:10.1109/ispsd.2015.7123389

Cited by 7 publications

(6 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, complex device structures are often introduced in these proposed technologies which make the industrial fabrication process very difficult and costly. Furthermore, even though device miniaturization is crucial for all voltage ranges, in the past few decades, most studies have been done on large LDMOS devices for mid-voltage and high-voltage applications [15][16][17][18][19][20][21][22][23][24][25][26][27]. And unfortunately, a thorough study on scaling of the planar LDMOS technology, limited to a straightforward planar device design, has not yet been performed.…”

Section: Introductionmentioning

confidence: 99%

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

Saadat

Put

Edwards

et al. 2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

We identify an optimum channel length for planar Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) field-effect transistors, in terms of the specific on-resistance, through systematic device simulation and optimization. We simulate LDMOS devices with different channel lengths ranging from 100 nm to 10 nm, modifying the length of the drift region and doping concentration of the body region to match a predetermined leakage current suitable for lowvoltage power applications (3.3V and 5V). For devices with a channel length exceeding 40 nm, reducing the channel length decreases the onresistance as expected. Below 40 nm, an increase in resistance is observed as the result of an increased body doping concentration leading to significant electron mobility degradation in the channel area.

show abstract

Section: Introductionmentioning

confidence: 99%

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

Saadat

Put

Edwards

et al. 2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

show abstract

“…However, under the same requirement of breakdown voltage (BV), a p-LDMOS usually has a larger specific on-resistance (R on,sp ) than an n-LDMOS. To address this problem, many structures such as the "double hole-conductive paths" and the "dual-channels for holes and electrons" have been proposed [4]- [7]. The effective utilization of electrons with high mobility in the "dual-channels for holes and electrons" leads to a smaller R on,sp than in the "double hole-conductive paths".…”

Section: Introductionmentioning

confidence: 99%

“…To achieve the simultaneous conductions for both holes and electrons, the proposed structure evolves from a previous p-LDMOS [8] for the acquirements of a voltage signal and a current signal. Compared with the previous works in this area [5]- [7], a different structure is utilized for a different method to control the n-channel gate in this work. The mechanism will be detailed in the following, and it should be noticed that only simulation results, no experimental results, are included.…”

Section: Introductionmentioning

confidence: 99%

A Novel p-LDMOS Additionally Conducting Electrons by Control ICs

Guo

Chen

2019

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

A silicon-on-insulator (SOI) p-channel lateral double-diffused MOSFET (p-LDMOS), conducting not only holes but also electrons, is proposed and investigated by TCAD simulations. Its most important advantage is the greatly improved relationship between the breakdown voltage (BV) and the specific on-resistance (R on,sp ). The improvement is mainly attributed to two aspects. First, many holes can accumulate in the p-drift region in the on-state, which provides a low-resistance path for hole conduction. Second, a paralleled n-LDMOS is, meanwhile, automatically triggered to form a new path for electrons. Electrons have higher mobility than holes; thus, the device performance is further improved. Based on a simulation comparison with the previous p-LDMOS at the same BV of 300 V, the R on,sp of the proposed p-LDMOS decreased by 78% and the figure of merit (FOM) increased approximately 3.4 times. Moreover, the proposed device still has the conventional three-terminal style, and its fabrication process is compatible with CMOS technology.INDEX TERMS High-side switch, power MOSFET, silicon-on-insulator.

show abstract

“…The LDMOSFET (Lateral Double‐diffused Metal‐Oxide‐Semiconductor Field‐Effect Transistor) has been widely used in Smart Power Integrated Circuits (SPICs) . The main concern for LDMOSFET is the tradeoff relationship between the breakdown voltage ( BV ) and the specific on‐resistance ( R s,on ) .…”

Section: Introductionmentioning

confidence: 99%

“…The LDMOSFET (Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor) has been widely used in Smart Power Integrated Circuits (SPICs). [1][2][3][4][5] The main concern for LDMOSFET is the tradeoff relationship between the breakdown voltage (BV) and the specific on-resistance (R s,on ). [6][7][8][9] At present, there have been two techniques used to increase the vertical BV for RESURF (REduced SURface Field) LDMOS.…”

Section: Introductionmentioning

confidence: 99%

The differences between N‐ and N+ buried layers in improving the breakdown voltage of RESURF LDMOSFETs

Wang

2019

Int J Numerical Modelling

View full text Add to dashboard Cite

The differences between N-and N+ buried layers in improving the breakdown voltage of RESURF (reduced surface field) LDMOSFETs (lateral doublediffused metal-oxide-semiconductor field-effect transistors) are discussed in this paper. Two concise RESURF criteria for LDMOS with a low-doped fully depleted N-buried layer (NBL) and a highly doped nondepleted N+ floating layer (NFL) are developed by optimizing the lateral and vertical electric fields.The analytical solution quantitatively demonstrates the variation of the drift charge concentration and its dependence on the key NBL and NFL parameters. It also indicates that the NBL LDMOS achieves a superior tradeoff between specific on-resistance (R s,on )and breakdown voltage (BV) to the NFL LDMOS. The BV 2 /R s,on for NBL LDMOS is 3.1 MW/cm 2 , which is increased respectively by 93.8% and 40.9% compared with the single RESURF and NFL-LDMOS. K E Y W O R D Sbreakdown voltage, LDMOS, on resistance, RESURF

show abstract

A RESURF P-N bimodal LDMOS suitable for high voltage power switching applications

Cited by 7 publications

References 8 publications

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

A Novel p-LDMOS Additionally Conducting Electrons by Control ICs

The differences between N‐ and N+ buried layers in improving the breakdown voltage of RESURF LDMOSFETs

Contact Info

Product

Resources

About