A reduced‐voltage differential signaling (RVDS) interface for chip‐on‐glass TFT‐LCD applications

Abstract

Abstract— Reduced‐voltage differential signaling (RVDS) is a novel interface for TFT‐LCD panels with a chip‐on‐glass (COG) structure, which has a point‐to‐point topology and a voltage mode differential signaling scheme. The voltage‐driving interface scheme has advantages in high‐speed operation owing to its relatively small time constant for the resistive channel condition. And reduced‐voltage signaling can reduce the power consumption of a transmitter. The display source driver IC with an RVDS interface, which is fabricated by using a 0.25‐μm CMOS process with a 2.5‐V logic supply voltage, offers a high data rate up to 500 Mbps, low‐current consumption of 2.2 mA, and good EMI characteristics. Also, an RVDS interface has programmable options that control the bandwidth, system power, and EMI performance. Therefore, the RVDS interface is a competitive solution for low‐power, low‐cost, and slim notebook applications.

40.2: An Improved Differential Signaling Scheme for the Chip‐On‐Glass Application of TFT‐LCD

“…For the transmitter of the timing controller, there are two different driving schemes for the COG application as shown in Figure 5. First, for the voltage driving scheme, the time constant of the interface channel with the voltage driving and voltage sensing scheme is smaller than the current driving and voltage sensing without source termination and then high-frequency data transmission is possible [2]. However, it is difficult to match the output impedance of the voltage-mode driver with the characteristic impedance of transmission lines on PCB because the series source termination is required for the voltage driver to eliminate reflection from the LOG.…”

“…A typical configuration of signaling scheme in the intra-panel interface for the COG application is shown in Figure 2. Because the frequency performance of the intra-panel interface is limited by LOG, there are several approaches to overcome the frequency bottleneck of the intra-panel interface of the LCM module [1], [2], [3]. In addition, reflections at the end of transmission line on PCB/FPC are unavoidable because it is difficult to adjust the characteristic impedance of LOG to the characteristic impedance of traces on PCB and FPC.…”

“…Various termination methods : (a) Source termination, (b) Load termination with current driver, and (c) Both source and load termination with voltage driver. Typical configuration of the intra-panel interface with the COG applicationZ TX,DIFF = Z C || (2R SW + 2Z SOURCE )  Z C(2) …”

A 1.4‐Gbps intra‐panel interface with low‐power and low‐EMI schemes for Tablet PC applications

“…However, highly resistive channel on glass severely limits the operation speed and degrades the EMI performance. To enhance the operation speed with COG technology, point‐to‐point interfaces such as reduced‐voltage differential signaling (RVDS) and low‐current differential signaling (LCDS) have been proposed. However, these interfaces have an inevitable skew issue due to the use of separate clock and data lines.…”

P‐40: Scalable Intra Panel Interface (SIPI™)—A point to Point Interface for LCDs

“…Conventional intra-panel interfaces with multi-drop topology such as Reduced Swing Differential Signaling (RSDS) [1] and mini Low voltage Differential Signaling (mini-LVDS) can't be applied to COG application because of high loss of glass substrate. So some point to point interfaces such as Reduced Voltage Differential Swing (RSDS) [2] and enhanced Reduced Voltage Differential Swing (eRSDS) [3] were proposed. However, RSDS has inevitable skew issue between lanes since data and clock are transmitted over heavily resistive line separately from TCON to SDs and eRVDS has RFI/EMI issue because the clock is still transmitted inside data.…”