The enhanced Reduced Voltage Differential Signaling (eRVDS) is a new intra-panel interface with clock embedded scheme forChip-On-Glass TFT-LCD panel. The source driver IC with eRVDS interface operates at higher data rate up to 720Mbps, lower power consumption, and lower EMI and reduces signal line to one third compared to conventional point-to-point COG interface.
A high-speed intra-panel interface with an enhanced reduced voltage differential signaling (eRVDS) scheme is implemented in a 0.18-μm high-voltage CMOS process for the chip-on-glass (COG) TFT-LCD applications. The proposed interface employs the zero-adjustable equalizer to enhance the maximum data rate, the early charge sharing scheme to improve the interface data transfer efficiency, and dynamic biasing technique to reduce a power consumption of the output buffers. Measured result demonstrates the maximum data rate of 1.4 Gbps from a 1.8-V supply voltage with a WQXGA 60-Hz COG TFT-LCD prototype panel.
An intra-panel interface system employing data scrambling for EMI suppression is presented in this work. The proposed data scrambler targets two sources of EMI found in a periodic clockembedded interface system: active data field and horizontal blanking period (HBP). For verification, an intra-panel interface based on enhanced Reduced Voltage Differential Signaling (eRVDS) with data scrambling function is implemented in CMOS technology, and EMI measurement of the prototype shows that suppression of data-induced EMI can be successfully achieved by the proposed scrambling technique.
-An intra-panel interface addressing all of the high-speed, low-power, and lowelectromagnetic interference (EMI) requirements for tablet personal computer applications is presented. This work proposes an adaptive clock window scheme to achieve 1.4-Gbps data-rate. For EMI suppression, data scrambling, horizontal blank period pattern scrambling, and novel clock and data recovery circuit are introduced. Lastly, for power-saving, the proposed interface dynamically biases source driver's output buffers and employs early charge sharing by controlling the configuration data. For verification, a WQXGA thin-film transistor liquid crystal display system is implemented with the timing controller and source driver ICs that are fabricated using 65-nm and 180-nm complementary metal-oxide semiconductor (CMOS) processes, respectively. The liquid crystal display system demonstrates maximum operation speed of 1.4 Gbps and suppression of EMI noise in LTE Band-20 and GSM 850 bands. The proposed power-saving schemes achieve 4.3% reduction in total power consumption by source driver IC, which reaches about 85% of power consumption by enhanced reduced-voltage differential signaling interface circuit.
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