A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things

Abstract

Abstract-Convolutional neural network (CNN) offers significant accuracy in image detection. To implement imagedetection using CNN in the internet of things (IoT) devices, a streaming hardware accelerator is proposed. The proposed accelerator optimizes the energy efficiency by avoiding unnecessary data movement. With unique filter decomposition technique, the accelerator can support arbitrary convolution window size. In addition, max pooling function can be computed in parallel with convolution by using separate pooling unit, thus achieving throughput improvement. A prototype accelerator was implemented in TSMC 65nm technology with a core size of 5mm 2 . The accelerator can support major CNNs and achieve 152GOPS peak throughput and 434GOPS/W energy efficiency at 350mW, making it a promising hardware accelerator for intelligent IoT devices.

Artificial Neural Networks-Based Machine Learning for Wireless Networks: A Tutorial

“…• User identification ⇒ DNN-based algorithm • Tracking accuracy improvement [125] • IoT devices management ⇒ SNN-based algorithm • Image detection [126] • Errors in collected data • Data relationship extraction ⇒ RNN-based RL algorithm • Data sampling [127] • Real-time training for ANNs • Modeling autonomous M2M communication ⇒ FNN and SNN based algorithm • Entity state prediction [128] • Target surveillance [129] environment. For example, a user displays only the visible portion of a 360 • video and, hence, transmitting the entire 360 • video frame can waste the capacity-limited bandwidth.…”

Lupulus: A Flexible Hardware Accelerator for Neural Networks

“…Finally, Table III compares similar accelerators, showing the process, the maximum frequency, the logic area, the amount of on-chip memory, the bit-width for inputs, and the GOPS (for reported frequency and normalized to 1 GHz). In terms of gate count and performance, Lupulus achieves the highest peak performance among the considered accelerators, at a 32 % and 39 % lower gate count compared to [5] and [8], respectively. However, we use 14 % more gates than [20] with only a 4 % improvement in GOPS/GHz.…”

“…Relation to Previous Work: Many existing accelerators, such as [5]- [8] have small local memories in the PEs for the weights, inputs, and partial sums, which may leave the local memories for the partial sums underutilized when partial sums are forwarded to a neighboring PE instead of being stored in the PE itself. Moreover, the partial sums may have to be read out to a high-level memory and then sent back later if the local memories are too small.…”

“…In our case, the partial sums are stored for groups of PEs, making it easier to fully utilize the memory for the partial sums. A similar architecture to Lupulus is [8], which also uses 3×3 blocks of PEs. However, for 1×1 convolutions, only two PEs out of nine can be turned on in [8], whereas our architecture can use all PEs.…”

An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)

“…EEP learning using convolutional and fully connected neural networks has achieved unprecedented accuracy on many modern artificial intelligence (AI) applications, such as image, voice, and DNA pattern detection and recognition [1][2][3][4][5][6][7][8][9][10]. However, one of the major problems that hinder its commercial feasibility is that neural networks require great computational resources and memory bandwidth even for very simple tasks.…”