An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)

Du, Yuan; Du, Li; Gu, Xuefeng; Du, Jieqiong; Wang, X. Shawn; Hu, Bonian; Jiang, Mengshi; Chen, Xiaoliang; Iyer, Subramanian S.; Chang, M.F.

doi:10.1109/tcad.2018.2859237

Cited by 36 publications

(21 citation statements)

References 42 publications

(43 reference statements)

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“…Charge-trapping memories have been typically used as synaptic devices to compose SNN circuits owing to their small cell area [17]. However, conventional charge-trapping memories require a high operation voltage, which leads to high power consumption.…”

Section: Non-volatile Tunnel Fet Memorymentioning

confidence: 99%

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

Kino

Fukushima

Tanaka

2020

IEEE J. Electron Devices Soc.

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Spiking neural networks (SNNs) have attracted considerable attention as next-generation neural networks. As SNNs consist of devices that have spike-timing-dependent plasticity (STDP) characteristics, STDP is one of the critical characteristics we need to consider to implement an SNN. In this study, we generated the STDP of a biological synapse with non-volatile tunnel-field-effect-transistor (tunnel FET) memory that has a charge-storage layer and a tunnel FET structure. Tunnel FET is a promising structure to reduce the operation voltage owing to its steep sub-threshold slope. Therefore, the non-volatile tunnel-FET memory we propose enables the implementation of low-operation-voltage SNNs. This paper reports the I-V, programing, and both symmetric and asymmetric STDP characteristics of a non-volatile tunnel-FET memory with p-channel-MOS-like operation.

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Section: Non-volatile Tunnel Fet Memorymentioning

confidence: 99%

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

Kino

Fukushima

Tanaka

2020

IEEE J. Electron Devices Soc.

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“…In addition to the traditional digital accelerator design, analog computing is also becoming one of the trends to improve the processor computation ability in solving machine learning problems. Here, we use the charge-trapping transistors (CTTs) technique as an example to introduce analog computing [14]. The complementary metal oxide semiconductor (CMOS)-compatible feature of the CTTs makes them very promising devices to implement large-sized computation using analog methodology.…”

Section: Analog Computingmentioning

confidence: 99%

“…Compared to traditional digital computation, analog computing shows tremendous advantages regarding the power, design cost, and computation speed. Among many analog computing systems, memristor-based ones have been widely reported [14]. Recently, more promising charge-trapping transistors (CTTs) were reported to be used as digital memory devices with reliable trapping and de-trapping behavior.…”

Section: Analog Computingmentioning

confidence: 99%

Hardware Accelerator Design for Machine Learning

Du¹,

Du²

2018

Machine Learning - Advanced Techniques and Emerging Applications

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Machinelearningiswidelyusedinmanymodernartificial intelligence applications. Various hardware platforms are implemented to support such applications. Among them, graphics processing unit (GPU) is the most widely used one due to its fast computation speed and compatibility with various algorithms. Field programmable gate arrays (FPGA) show better energy efficiency compared with GPU when computing machine learning algorithm at the cost of low speed. Finally, various application specific integrated circuit (ASIC) architecture is proposed to achieve the best energy efficiency at the cost of less reconfigurability which makes it suitable for special kinds of machine learning algorithms such as a deep convolutional neural network. Finally, analog computing shows a promising methodology to compute large-sized machine learning algorithm due to its low design cost and fast computing speed; however, due to the requirement of the analog-to-digital converter (ADC) in the analog computing, this kind of technique is only applicable to low computation resolution, making it unsuitable for most artificial intelligence (AI) applications.

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“…Artificial neural network (ANN)-based machine learning, known as a promising technology, has been researched widely to enable electronic devices more intelligent and efficient [ 1 , 2 , 3 , 4 ]. ANN is inspired by the brain of living creatures, which contains components such as neurons, connections, weights, and a propagation function.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks

Geng

Sun

Nakatake

2020

Sensors

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Perceptron is an essential element in neural network (NN)-based machine learning, however, the effectiveness of various implementations by circuits is rarely demonstrated from chip testing. This paper presents the measured silicon results for the analog perceptron circuits fabricated in a 0.6 μm/±2.5 V complementary metal oxide semiconductor (CMOS) process, which are comprised of digital-to-analog converter (DAC)-based multipliers and phase shifters. The results from the measurement convinces us that our implementation attains the correct function and good performance. Furthermore, we propose the multi-layer perceptron (MLP) by utilizing analog perceptron where the structure and neurons as well as weights can be flexibly configured. The example given is to design a 2-3-4 MLP circuit with rectified linear unit (ReLU) activation, which consists of 2 input neurons, 3 hidden neurons, and 4 output neurons. Its experimental case shows that the simulated performance achieves a power dissipation of 200 mW, a range of working frequency from 0 to 1 MHz, and an error ratio within 12.7%. Finally, to demonstrate the feasibility and effectiveness of our analog perceptron for configuring a MLP, seven more analog-based MLPs designed with the same approach are used to analyze the simulation results with respect to various specifications, in which two cases are used to compare to their digital counterparts with the same structures.

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An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)

Cited by 36 publications

References 42 publications

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

Hardware Accelerator Design for Machine Learning

Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks

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