A real-time center-of-mass tracker circuit implemented by neuron MOS technology

Abstract

A new-architecture integrated circuit has been developed as a key element of a system that can real-time track the center of mass of an moving image on a two-dimensional (2-D) pixel array. The circuit has been implemented using a high-functionality transistor called neuron MOSFET (neuMOS or MOS for short), hence having a very simple circuit configuration. A quasi-two-dimensional algorithm is assumed for system in the circuit. A one-dimensional (1-D) array of neuron MOS circuits automatically finds the center-of-mass location using the image intensity distribution projected onto x x x or y y y axis. The unique feature of the circuit is that it accepts analog inputs without A/D conversion but produces binary outputs, thus providing a very smooth interfacing between the real world and digital systems. Test circuits have been fabricated by a double-polysilicon CMOS process and their operation has been experimentally demonstrated.Index Terms-Center of mass, neuron MOS, source follower.

Hybrid dual‐complementary metal–oxide–semiconductor/memristor synapse‐based neural network with its applications in image super‐resolution

“…Also, it shows excellent linearity with time t during weight programming. The relevant slope can be computed based on (9) and (10).…”

“…Meanwhile, the circuit design of the biological synapse is another primary factor limiting the hardware implementation of ANNs. In analogue implementation schemes, conventional synaptic circuits are mostly constituted by resistors [6, 7], capacitors [8], and complementary metal–oxide–semiconductor (CMOS) transistors [9, 10]. Specifically, the weights of the resistor‐based synapses are fixed values once the synaptic circuits are fabricated, which means the weight variation (during the training process) is not allowed unless the interconnected resistors can be replaced.…”

A bio-inspired apposition compound eye machine vision sensor system

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A Minimum Hamming Distance Search Associative Memory Using Neuron CMOS Inverters

“…The proposed circuit excludes the influence of the variation of the initial charge of floating gate and the threshold voltage of transistor by connecting the output of neuron CMOS inverter and floating gate prior to searching operation, which causes the floating gate voltage and the threshold voltage of neuron CMOS inverter to be equal. The circuits described in reference [9,10] adopt the same method described above, which excludes the influence of the initial charge of floating gate, but these circuits need neuron MOS source follower and neuron CMOS inverter, and they also need to increase the coupling capacitance of MOS proportional to the input number. However, the proposed circuit does not require neuron MOS source follower circuit, and it can further adopt the minimum capacitance as the coupling capacitance of all of the neuron CMOS inverters.…”