A Quiescent 407-nA Output-Capacitorless Low-Dropout Regulator With 0–100-mA Load Current Range

Jiang, Yushan; Wang, Dong; Chan, P.K.

doi:10.1109/tvlsi.2018.2890698

Cited by 19 publications

(14 citation statements)

References 28 publications

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“…LDO linear regulator, which does not require any energy storage component, is adequate for extremely small solutions. Moreover, recent developments proposed low quiescent current control schemes in both analog 82–85 and digital 86–88 domains. Additionally, output capacitor‐less topologies further push the area constraint of an LDO regulator to be negligible in a system 89–91 .…”

Section: Integrated Power Convertersmentioning

confidence: 99%

Bird's‐eye view of analog and mixed‐signal chips for the 21st century

Martins

Mak

Chan

et al. 2021

Circuit Theory & Apps

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SUMMARY The Internet of Everything (IoE), clearly a 21st century's technology, brilliantly plays with digital data obtained from analog sources, bringing together two different realities, the analog (physical/real), and the digital (cyber/virtual) worlds. Then, with the boundaries of IoE still analog in nature, the required functions at the interface involve sensing, measuring, filtering, converting, processing, and connecting, which imply that the analog layer governs the entire system in terms of accuracy and precision. Furthermore, such interface integrates several analog and mixed‐signal subsystems that comprise mainly signal transmission and reception, frequency generation, energy harvesting, data, and power conversion. This paper sets forth a state‐of‐the‐art design perspective of some of the most critical building blocks used in the analog/digital interface, covering wireless cellular transceivers, millimeter‐wave frequency generators, energy harvesting interfaces, plus, data and power converters, that exhibit high quality performance achieved through low‐power consumption, high energy‐efficiency, and high speed.

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Section: Integrated Power Convertersmentioning

confidence: 99%

Bird's‐eye view of analog and mixed‐signal chips for the 21st century

Martins

Mak

Chan

et al. 2021

Circuit Theory & Apps

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“…For SoC application, removal of the off-chip capacitor can reduce the area of the printed circuit board (PCB) and the number of I/O pads on the chip, which is significantly beneficial in terms of integration. Therefore, in recent years, fully integrated LDO (or OCL-LDO) regulators have been widely studied and reported [ 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 ]. The output load capacitor

mainly comes from parasitics of the power line, which is generally modeled from a few decades to 100 pF, and several orders lower than the off-chip capacitor.…”

Section: Introductionmentioning

confidence: 99%

A Fully Integrated Low-Dropout Regulator with Improved Load Regulation and Transient Responses

Chen

et al. 2022

Micromachines

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A fully integrated low-dropout (LDO) regulator with improved load regulation and transient responses in 40 nm technology is presented in this paper. Combining adjustable threshold push-–pull stage (ATPS) and master–slave power transistors topology, the proposed LDO maintains a three-stage structure within the full load range. The proposed structure ensures the steady-state performance of LDO and achieves 0.017 mV/mA load regulation. The ATPS consumes little quiescent current at light load current condition, and the turn-on threshold of the ATPS can be adjusted by a current source. Once the value of current source is set, the turn-on threshold is also determined. A benefit of the proposed structure is that the LDO can be stable from 0 to 100 mA load current with a maximum 100 pF parasitic load capacitance and a 0.7 pF compensation capacitor. It also shows good figure of merit (FOM) without an extra transient enhanced circuit. For the maximum 100 mA load transient with 100 ns edge time, the undershoot and overshoot are less than 33 mv. The dropout voltage of the regulator is 200 mV with input voltage of 1.1 V. The total current consumption of the LDO was 24.6 μA at no load.

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“…For SoC application, removal of the off-chip capacitor can reduce the area of the printed circuit board (PCB) and the number of I/O pads on the chip, which is significantly beneficial in terms of integration. So, in recent years, OCL-LDO regulators are widely studied and reported [1][2][3][4][5][6][7][8]. Since the off chip capacitor is removed, the major performance requirements of the LDO will inevitably degrades, such as transient response.…”

Section: Introductionmentioning

confidence: 99%

“…However, the load current is only 10 mA and the LDO requires an on-chip capacitance of 120 pF. Masterslave power transistors topology is used in [1,2], the LDO in which transform themself between 2-stage and 3-stage cascaded topology at different load conditions. They can achieve ultra low power consumption and good transient response.…”

Section: Introductionmentioning

confidence: 99%

“…So an adjustable threshold push-pull stage (ATPS) is proposed in this paper shown in 𝜇A, the ATPS turns on and two power transistors work together to provide load current. Compared with [1,2], the structure proposed in this letter maintains a 3-stage structure within the full load range rather than 2-stage or 3-stage cascaded topology at different load conditions. The proposed structure ensures the steady-state performance of LDO such as load regulation.…”

Section: Introductionmentioning

confidence: 99%

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A Fast-Transient Output-Capacitorless LDO Regulator With Master-Slave Power Transistors

Chen

et al. 2022

Preprint

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A fast-transient output-capacitorless (OCL) low-dropout (LDO) regulator with adjustable threshold push–pull stage (ATPS) and master-slave power transistors topology is presented in this paper. The ATPS consumes little quiescent current at light load current condition and the turn on threshold of the proposed ATPS can be adjusted by a current source. With the ATPS and master-slave power transistor topology, the proposed LDO can be stable from 0 to 100 mA load current at a maximum 100 pF parasitic load capacitance and a 0.7 pF compensation capacitor. It shows good figure of merit (FOM) without extra transient enhanced circuit. For the maximum 100 mA load transient with 100 ns edge time, the undershoot and overshoot are less than 33 mv.

show abstract

A Quiescent 407-nA Output-Capacitorless Low-Dropout Regulator With 0–100-mA Load Current Range

Cited by 19 publications

References 28 publications

Bird's‐eye view of analog and mixed‐signal chips for the 21st century

Bird's‐eye view of analog and mixed‐signal chips for the 21st century

A Fully Integrated Low-Dropout Regulator with Improved Load Regulation and Transient Responses

A Fast-Transient Output-Capacitorless LDO Regulator With Master-Slave Power Transistors

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