A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience

Li, Y. Q.; Wang, H. B.; Liu, R.; Chen, L.; Nofal, Issam; Shi, Shuting; He, A.-L.; Guo, Gang; Baeg, Sanghyeon; Wen, Shi-Jie; Wong, Rick; Chen, M.; Wu, Qiong

doi:10.1109/tns.2017.2704062

Cited by 51 publications

(33 citation statements)

References 26 publications

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“…In order to examine the validity of the laser SEU mapping results, 10T Quatro cell simulation has been conducted on the 65 nm CMOS process model by using IROC TFIT tool.The similar device model is created and calibrated in previous [31,32,33]. As shown in Figure 11, TFIT simulation results are obtained with the LET from 0.01 to 0.50 pC/μm for “00H” and “FFH” data pattern respectively.…”

Section: Resultsmentioning

confidence: 99%

Application of Two-Photon-Absorption Pulsed Laser for Single-Event-Effects Sensitivity Mapping Technology

Chen

Belev

et al. 2019

Materials

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Single-event effects (SEEs) in integrated circuits and devices can be studied by utilizing ultra-fast pulsed laser system through Two Photon Absorption process. This paper presents technical ways to characterize key factors for laser based SEEs mapping testing system: output power from laser source, spot size focused by objective lens, opening window of Pockels cell, and calibration of injected laser energy. The laser based SEEs mapping testing system can work in a stable and controllable status by applying these methods. Furthermore, a sensitivity map of a Static Random Access Memory (SRAM) cell with a 65 nm technique node was created through the established laser system. The sensitivity map of the SRAM cell was compared to a map generated by a commercial simulation tool (TFIT), and the two matched well. In addition, experiments in this paper also provided energy distribution profile along Z axis that is the direction of the pulsed laser injection and threshold energy for different SRAM structures.

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Section: Resultsmentioning

confidence: 99%

Application of Two-Photon-Absorption Pulsed Laser for Single-Event-Effects Sensitivity Mapping Technology

Chen

Belev

et al. 2019

Materials

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“…To mitigate SNUs, DNUs, TNUs, and/or SETs, by means of radiation-hardening-by-design (RHBD) approaches, many hardened storage cells such as static random access memories (SRAMs) [9][10][11][12], flip-flops [13][14][15][16], and latches [5][6][7][8][17][18][19][20][21][22][23][24][25][26][27], have been proposed. This paper focuses on latches.…”

Section: Introductionmentioning

confidence: 99%

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications

Yan

Feng

Zhao

et al. 2020

2020 57th ACM/IEEE Design Automation Conference (DAC)

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This paper proposes a cost-effective, high-impedancestate (HIS)-insensitive, triple-node-upset (TNU)-tolerant and single-event-transient (SET)-filterable latch, namely HITTSFL, to ensure high reliability with low-cost. The latch mainly comprises an output-level SET-filterable Schmitt-trigger and three inverters that make the values stored in three parallel single-node-upset (SNU)-recoverable dual-interlocked-storagecells (DICEs) converge at a common node to tolerate any possible TNU. The latch does not use C-elements to be insensitive to the HIS. Simulation results demonstrate the TNU-tolerability and SET-filterability of the proposed HITTSFL latch. Moreover, due to the use of clock-gating technologies and fewer transistors, the proposed latch can reduce delay, power, and area by 76.65%, 6.16%, and 28.55%, respectively, compared with the state-of-theart TNU hardened latch (TNUHL) that cannot filter SETs.

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“…To mitigate SNUs or even DNUs, many designs of SRAM cells [4,[6][7][8][9][10][11][12][13][14][15] have been proposed by using the Radiation Hardening By Design (RHBD) approach. RHBD, which is also used for designing latches [16][17] and flip-flops [18][19][20], can effectively mitigate the impact of radiation particles on SRAM cells. The traditional SRAM cell is called 6T since it consists of 6 transistors including 2 PMOS and 2 NMOS transistors for value-retention and 2 NMOS transistors for access operations.…”

Section: Introductionmentioning

confidence: 99%

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors

Dou

Yan

Zhou

et al. 2020

2020 IEEE International Test Conference in Asia (ITC-Asia)

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In this paper, a highly reliable SRAM cell, namely SESRS cell, is proposed. Since the cell has a special feedback mechanism among its internal nodes and has more access transistors compared to a standard SRAM cell, the SESRS cell provides the following advantages: (1) it can self-recover from single node upsets (SNUs) and double-node upsets (DNUs); (2) it can reduce power consumption by 49.78% and silicon area by 7.92%, compared with the only existing SRAM cell which can self-recover from all possible DNUs. Simulation results validate the robustness of the proposed SESRS cell. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed SESRS cell can reduce read access time by 61.93% on average.

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A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience

Cited by 51 publications

References 26 publications

Application of Two-Photon-Absorption Pulsed Laser for Single-Event-Effects Sensitivity Mapping Technology

Application of Two-Photon-Absorption Pulsed Laser for Single-Event-Effects Sensitivity Mapping Technology

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors

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