A quarter-micron CMOS, 1 GHz VCO/prescaler-set for very low power applications

Pfaff, D.; Huang, Qiuting

doi:10.1109/cicc.1999.777364

Cited by 22 publications

(2 citation statements)

References 10 publications

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“…NAND and OR gates are incorporated into synchronous flip-flops to save power [6]. Sine the supply is limited to 1.2V, the internal swing of each stage is set to be 200mV (single-ended peak voltage), and all stages are DC coupled without level converters.…”

Section: Prescaler-by-64/65mentioning

confidence: 99%

A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13μm CMOS

Chen

Huang

2005

Proceedings of the 2005 International Symposium on Low Power Electronics and Design - ISLPED '05

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A 4GHz integer-N frequency synthesizer is realized in a 0.13µm CMOS technology. It has a 400kHz reference frequency and 40kHz loop bandwidth such that 2GHz quadrature LO signals can be generated after a divide-by-two, with channel raster of 200kHz. The measured in-band phase noise is -74dBc/Hz @4kHz offset. A self-regulated charge pump is proposed to improve matching as well as charge sharing. Reference spurs are thereby kept below -55dBc over the VCO tuning voltage from rail to rail. The requirements for UMTS transceiver have been fulfilled with an overall power consumption of 9.5mW, which is the lowest reported to date. Core area of the chip is as small as 0.2mm 2 .

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Section: Prescaler-by-64/65mentioning

confidence: 99%

A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13μm CMOS

Chen

Huang

2005

Proceedings of the 2005 International Symposium on Low Power Electronics and Design - ISLPED '05

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“…FDs can be realized using Common Mode Logic (CML) [6], [7], dynamic logic [8], Miller dividers [9] and Injection Locked Frequency Dividers (ILFD) [10]. The use of digital frequency dividers is constrained at high frequencies by their high power consumption, which increases rapidly with frequency [11].…”

Section: Introductionmentioning

confidence: 99%

An LC CMOS injection-locked frequency divider for divide-by-two and divide-by-three operation

Asghar¹,

Awan²,

Huang

et al. 2013

2013 European Conference on Circuit Theory and Design (ECCTD)

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Numerous circuit topologies have been proposed for divide-by-m injection-locked frequency dividers (ILFDs), most of which have been optimized for division by even numbers, especially divide-by-2. It has been more difficult to realize division by odd numbers, such as divide-by-3. This paper describes a CMOS injection locked frequency divider (ILFD) that can operate equally well in both divide-by-two and divide-by-three modes. The ILFD is based on a cross-coupled CMOS LC-tank oscillator having capacitive and direct injection via both NMOS and PMOS transistors connected across the LC tank. The circuit is similar to a conventional CMOS ILFD for divide-by-two operation with direct injection, but it combines the effects of two independent injection techniques to maximize the width of its divide-by-three locking range. The paper presents the circuit architecture, SPICE simulations, and experimental measurements.

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