A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13μm CMOS

Chen, Xinhua; Huang, Qiuting

doi:10.1145/1077603.1077620

Cited by 4 publications

(1 citation statement)

References 10 publications

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“…Instead, fractional-N architecture is used because the output frequency can be a fraction of the reference frequency. 5,6 On the other hand, 60 GHz RF communications has a very wide channel bandwidth. Namely 7 GHz from 57 GHz to 64 GHz is available for communication.…”

Section: Integer-n Architecturementioning

confidence: 99%

A SiGe 6 modulus prescaler for a 60 GHz frequency synthesizer

Kamal

Zhu

Al-Sarawi

et al. 2007

Microelectronics: Design, Technology, and Packaging III

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A prescaler is widely used in frequency synthesizers in order to handle channel selection. The division ratio has to be chosen carefully to achieve the desired frequency. In this paper, we present a 6 modulus prescaler in a 0.18 µm SiGe BiCMOS technology. The prescaler is part of a 60 GHz frequency synthesizer. In addition, we present a frequency planning for the 60 GHz frequency synthesizer. The prescaler employs an integer-N architecture. The circuit has a programmable divider with a division ratio of 7 and 8 and two counters to control the division ratio. The programmable divider utilizes ECL circuits, while the counters utilise CMOS circuits. Therefore an ECL-to-CMOS converter is used to bridge these two kinds of circuits. Simulation results show that the prescaler operates up to 4 GHz from a 1.8 V supply voltage.

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Section: Integer-n Architecturementioning

confidence: 99%

A SiGe 6 modulus prescaler for a 60 GHz frequency synthesizer

Kamal

Zhu

Al-Sarawi

et al. 2007

Microelectronics: Design, Technology, and Packaging III

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A 5-GHz CMOS Type-II PLL With Low $K_{\rm VCO}$ and Extended Fine-Tuning Range

Bruss

Spencer

2009

IEEE Trans. Microwave Theory Techn.

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Bottom-k sketches

Cohen

Kaplan

2007

Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems

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A Bottom-sketch is a summary of a set of items with nonnegative weights. Each such summary allows us to compute approximate aggregates over the set of items. Bottom-sketches are obtained by associating with each item in a ground set an independent random rank drawn from a probability distribution that depends on the weight of the item. For each subset of interest, the bottom-sketch is the set of the minimum ranked items and their ranks. Bottomsketches have numerous applications. We develop and analyze data structures and estimators for bottom-sketches to facilitate their deployment. We develop novel estimators and algorithms that show that they are a superior alternative to other sketching methods in both efficiency of obtaining the sketches and the accuracy of the estimates derived from the sketches.

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A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13μm CMOS

Cited by 4 publications

References 10 publications

A SiGe 6 modulus prescaler for a 60 GHz frequency synthesizer

A SiGe 6 modulus prescaler for a 60 GHz frequency synthesizer

A 5-GHz CMOS Type-II PLL With Low $K_{\rm VCO}$ and Extended Fine-Tuning Range

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