A high frequency “divide-by-odd number” CMOS LC injection-locked frequency divider

Kennedy, Michael Peter; Awan, Muhammad Asfandyar; Asghar, Malik Summair

doi:10.1007/s10470-013-0197-5

Cited by 2 publications

(2 citation statements)

References 27 publications

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“…The communication signalling between two conventional 3 Such clock frequency division can be realized easily using injection-locked frequency dividers (ILFDs). Most of ILFDs have been optimized for division by even numbers [28].…”

Section: E Communication Procedures Between Two Conventional 3d Routersmentioning

confidence: 99%

A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias

Said

Shalaby

Mehdipour

et al. 2016

Microprocessors and Microsystems

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Abstract-The use of short Through-Silicon Vias (TSVs) in 3D integration Technology introduces a significant reduction in routing area, power consumption, and delay. Although, there are still several challenges in 3D integration technology; mainly low yield, which is a direct result of extra fabrication steps of TSVs. Therefore, reducing TSV count has a considerable effect on improving yield and hence reducing cost. A TSV multiplexing technique called TSVBOX was introduced in [1] to reduce the TSV count without affecting the direct benefits of TSVs. Although, the TSVBOX introduces some delay to the signals to be multiplexed, this delay effect of TSV multiplexing is not addressed yet. In this paper, we analyze the TSVBOX timing requirements and propose a design methodology for TSVBOXbased 3D Network-on-Chip (NoC). Then performance and power comparisons are conducted to investigate the direct effects of TSV multiplexing on these two metrics. After that the basic fabrication metrics are compared to investigate the effect of the proposed design methodology on yield and cost. We show that the TSVBOX extremely enhances the fabrication metrics at minimal degradation in performance and power consumption, especially for Hotspot-like traffic patterns.

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Section: E Communication Procedures Between Two Conventional 3d Routersmentioning

confidence: 99%

A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias

Said

Shalaby

Mehdipour

et al. 2016

Microprocessors and Microsystems

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show abstract

“…Injection locked dividers (ILDs) offer highfrequency operation at low powers at the expense of a limited locking range [3]. ILDs offer also only static (usually divideby-2 per inductor, with some recent circuits also supporting divide-by-3 operation without additional inductors, see [4]) division ratios. Digital dividers offer robust operation with a wide range of divider ratios, which can be programmable.…”

Section: Introductionmentioning

confidence: 99%

A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS

Krishna

Jain

Quadir

et al. 2014

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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We present a multi-modulus frequency divider based upon novel dual-modulus 4/5 and 2/3 true single-phase clocked (TSPC) prescalers. High-speed and low-power operation was achieved by merging the combinatorial counter logic with the flip-flop stages and removing circuit nodes at the expense of allowing a small short-circuit current during a short fraction of the operation cycle, thus minimizing the amount of nodes in the circuit. The divider is designed for operation in wireline or fibreoptic serial link transceivers with programmable divider ratios of 64, 80, 96, 100, 112, 120 and 140.The divider is implemented as part of a phase-locked loop around a quadrature voltage controlled oscillator in a 65nm CMOS technology. The maximum operating frequency is measured to be 17GHz with 2mW power consumption from a 1.0V supply voltage, and occupies 25x50m 2 . Keywords-Multi-modulus divider, frequency divider, prescaler, true single-phase clocked (TSPC) logicI.

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A high frequency “divide-by-odd number” CMOS LC injection-locked frequency divider

Cited by 2 publications

References 27 publications

A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias

A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias

A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS

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