A Quantization Noise Suppression Technique for<tex>$DeltaSigma$</tex>Fractional-<tex>$N$</tex>Frequency Synthesizers

Programmable CMOS injection-locked frequency divider

“…Although some multimode ILFDs have been proposed, their division ratios are changed by injection signal in different ports [3] or by varying the frequency of the injection signal [4]. Since the moduli of these dividers are not really programmable, when they are used in integer-N PLLs, the frequency resolution will be increased, while in fractional-N PLLs, their quantisation noise will be degraded [5]. To utilise the high-speed property and resolve the above-mentioned issue of ILFDs, in this Letter, we present a programmable divide-by-6/7 ILFD by using a phaseswitching technique.…”

A tool for power and phase noise optimization in frequency synthesizers

“…14 This Work [16] [13] [12] Fig. 15 Phase noise and power comparison at 10, 100 kHz, 1 and 10 MHz offset frequencies the overall synthesizer consumes as little as 4.27 mW in total with no building blocks over-designed.…”

“…8 based on an averaged survey of [11,12,15,25] and [26]. Thus, we perform optimization focusing on these two blocks.…”

“…In a low phase noise and low power constrained system, overdesign in any of the blocks is a waste of power. Due to the lack of an optimization technique at the synthesizer level, designers often rely on their experience and intuition for good synthesizer designs [11][12][13][14][15][16][17].…”

A novel topology for modular frequency dividers with enhanced speed and power efficiency

“…In most of published works, current mode logic (CML) [2,3] or dynamic logic [4,[6][7][8][9][10][11][12][13][14][15][16] has been used in design of dividers. While CML based dividers can achieve high speed and even work with low-amplitude input signals; their static power dissipation limits use of them for power-conscious applications.…”