A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons

Chang, Cheng-Shang; Chen, Jiawei; Chang, Hsiu-Cheng; Yang, Yao-Chang; Wang, Jinn‐Shyan; Guo, Jiun-In

doi:10.1109/sips.2007.4387602

Cited by 5 publications

(5 citation statements)

References 6 publications

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“…Chang et al [7] propose a quality-scalable intra-frame encoder. They propose three fast algorithms: a context-correlation search algorithm (CC-SA), a probability-context-correlation search algorithm (PCC-SA), and a quarter-macroblock search algorithm (QMB-SA), to speed up the encoding loop.…”

Section: Related Workmentioning

confidence: 99%

“…The authors of Ref. [7] further improve the encoder to support 1080p video. The improved encoder [12] can encode 1080p video at 30 fps when running at 152 MHz.…”

Section: Related Workmentioning

confidence: 99%

“…Table 8 shows the performance of the proposed intra-frame encoder compared to previous works including intra-frame encoders (coder) and intra-frame encoding loop designs (loop). The performance of Reference [7] and Reference [12] are obtained using the quality level QS2. The proposed design can encode 30 fps 1080p video when running at 108 MHz and consuming only 19.8 mW.…”

Section: Tablementioning

confidence: 99%

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VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding

Kuo

Lin

2013

IPSJ Transactions on System LSI Design Methodology

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Intra-frame encoding is useful for many video applications such as security surveillance, digital cinema, and video conferencing because it supports random access to every video frame for easy editing and has low computational complexity that results in low hardware cost. H.264/AVC, which is the most popular video coding standard today, also defines novel intra-coding tools to achieve high compression performance at the expense of significantly increased computational complexity. We present a VLSI design for H.264/AVC intra-frame encoder. The paper summaries several novel approaches to alleviate the performance bottleneck caused by the long data dependency loop among 4 × 4 luma blocks, integrate a high-performance hardwired CABAC entropy encoder, and apply a clock-gating technique to reduce power consumption. Synthesized with a TSMC 130 nm CMOS cell library, our design requires 194.1 K gates at 108 MHz and consumes 19.8 mW to encode 1080p (1920 × 1088) video sequences at 30 frames per second (fps). It also delivers the same video quality as the H.264/AVC reference software. We suggest a figure of merit called Design Efficiency for fair comparison of different works. Experimental results show that the proposed design is more efficient than prior arts.

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Section: Related Workmentioning

confidence: 99%

“…The authors of Ref. [7] further improve the encoder to support 1080p video. The improved encoder [12] can encode 1080p video at 30 fps when running at 152 MHz.…”

Section: Related Workmentioning

confidence: 99%

Section: Tablementioning

confidence: 99%

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VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding

Kuo

Lin

2013

IPSJ Transactions on System LSI Design Methodology

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“…It reduces 32 cycles as compared to the design using 1-D Hadamard transform. To reduce the hardware cost, we integrate the DCT, IDCT and Hadamard transform together into a multi-transform unit and optimize the IPG with the hardware sharing mechanisms including the shared item mechanism of intra pixel generator (SIMIPG) and plane mode sharing mechanism (PMSM) [34]. In addition, although the plane mode in H.264 intra-coding is complex, we realize it by sharing the IPG hardware for improving the video quality.…”

Section: Intra-codingmentioning

confidence: 99%

A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications

Chang

Chen

et al. 2009

IEEE Trans. Circuits Syst. Video Technol.

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This paper proposes a dynamic quality-adjustable H.264 baseline profile (BP) video encoder that comprises 470 Kgates and 13.3 kB SRAM in a core size of 4.3 × 4.3 mm 2 using TSMC 0.13 m 1P8M CMOS technology. Exploiting parameterized algorithms for motion estimation and intra prediction, the proposed design can dynamically configure the encoding modes with the design trade-off between power consumption and video quality for various video encoding applications. In addition, the proposed basic unit (BU)-based rate control hardware can maintain a constant and stable bit rate for network video transmission. It achieves real-time H.264 video encoding on CIF, D1, and HD720@30 frames/s with 7 mW to 25 mW, 27 mW to 162 mW, and 122 mW to 183 mW power dissipation in different quality modes. Index Terms-Baseline profile, H.264, HD720, qualityadjustable, video encoder.

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“…An approach with two intra prediction units was presented in [5] to further increase the throughput for 720p encoding. The proposal presented in [6] reduced the complexity by supporting distinct image quality levels, with a small quality drop. An architecture with two intra prediction units and a new prediction order for 4x4 blocks supporting HD1080p is presented in [7].…”

Section: Introductionmentioning

confidence: 99%

A high throughput H.264/AVC intra-frame encoding loop architecture for HD1080p

Diniz

Thiele

Susin

et al. 2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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In this work we present a high throughput hardware architecture for the H.264/AVC intra-frame encoder exploiting the parallelism of intra prediction, forward and inverse transforms and quantization. Since there is a strong data dependency between the intra prediction and the image reconstruction loop, the latency of this path is a key design issue in order to provide high performance coding. Considering that 77% of the total intra-encoding computation is spent in these modules, our architecture handles a 4-pixel wide intra prediction module and a 16-pixel wide reconstruction loop. Compared to the state-of-the-art our approach reduces by 47% the number of cycles to process a macroblock. Running at 150 MHz our architecture guarantees encoding of 61 HD1080p frames per second. The developed architecture requires 73.4 MHz to real-time encode HD1080p, which is a 46% reduction of the frequency requirement compared to the state-of-the-art.

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A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons

Cited by 5 publications

References 6 publications

VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding

VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding

A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications

A high throughput H.264/AVC intra-frame encoding loop architecture for HD1080p

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