A high throughput H.264/AVC intra-frame encoding loop architecture for HD1080p

Diniz, Cláudio M.; Thiele, Cristiano; Susin, Altamiro; Bampi, Sérgio; Sampaio, Felipe; Palomino, Daniel; Agostini, Luciano

doi:10.1109/iscas.2011.5937631

Cited by 12 publications

(11 citation statements)

References 11 publications

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“…Its samplegeneration rate is equal to 16, which is the highest among the designs. Figure 4 shows that if we remove either 4×4 or 8×8 intra predictions as in [5,6], the number of clock cycles per macroblock for low-delay reconstructions loop decreases close to the state-of-the-art. The architecture described in [9] needs only 160 cycles per macroblock.…”

Section: Implementation Results and Conclusionmentioning

confidence: 77%

“…The comparison shows that the proposed intra predictor is slightly larger than some other designs [2][3][4]. However, the proposed supports both the Plane mode and intra 8×8 whereas other designs support only one [3,[5][6][7] or neither of them [2,4]. Moreover, the proposed architecture supports all chroma formats and multi-QP coding for 4×4 and 8×8 modes.…”

Section: Implementation Results and Conclusionmentioning

confidence: 96%

“…In practice, it is indispensible to apply a little higher frequencies to take into account encoder-level control and inter mode processing. Apart from [6], the reference designs cooperate with off-chip memories to save pixel line from the upper macroblocks, and some of them [2][3][4] assume the controller external to the intra predictor. These features involve the use of additional resources not taken into account in Table 2.…”

Section: Implementation Results and Conclusionmentioning

confidence: 99%

“…In literature, there are some architectures of the H.264/AVC encoder intra prediction [2][3][4][5][6][7][8][9][10][11][12][13][14]. However, none of them supports all intra prediction modes available in High Profile.…”

Section: Introductionmentioning

confidence: 99%

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Intra Prediction for the Hardware H.264/AVC High Profile Encoder

Roszkowski

Pastuszak

2013

J Sign Process Syst

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The hardware implementation of the intra prediction described in this paper allows the H.264/AVC encoder to achieve optimal compression efficiency in real-time conditions. The architecture has some features that distinguish it from other solutions described in literature. Firstly, the architecture supports all intra prediction modes defined in High Profile of the H.264/AVC standard for all chroma formats. Secondly, the architecture can generate predictions for several quantization parameters. Thirdly, the hardware cost is reduced as the same resources are used to compute prediction samples for all the modes. Fourthly, the high sample-generation rate enables the encoder to achieve high throughputs. Fifthly, 4×4 block reordering and interleaving with other modes minimize the impact of the long-delay reconstruction loop on the encoder throughput. The architecture is verified against the JM.12 reference model and within the real-time FPGA hardware encoder. The synthesis results show that the design can operate at 100 MHz and 200 MHz for FPGA Aria II and 0.13 μm TSMC technology, respectively. These frequencies allow the encoder to support 720p and 1080p video at 30 fps.

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Section: Implementation Results and Conclusionmentioning

confidence: 77%

Section: Implementation Results and Conclusionmentioning

confidence: 96%

Section: Implementation Results and Conclusionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Intra Prediction for the Hardware H.264/AVC High Profile Encoder

Roszkowski

Pastuszak

2013

J Sign Process Syst

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“…A number of hardware implementations of H.264/AVC encoders have been developed [7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. Some of them [7][8][9][10][11][12][13] are dedicated only for intra coding and cannot achieve high compression efficiencies.…”

Section: Introductionmentioning

confidence: 99%

Architecture Design of the H.264/AVC Encoder Based on Rate-Distortion Optimization

Pastuszak

2015

IEEE Trans. Circuits Syst. Video Technol.

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The rate-distortion optimization allows video encoders to achieve better compression efficiencies due to more reliable mode decisions. On the other hand, this technique involves a high computational cost when actual rates and distortions are estimated. In order to achieve real-time processing, video encoders apply simplified algorithms for mode decisions. This paper presents the H.264/AVC encoder architecture which benefits from the rate-distortion optimization and achieves high throughputs. To access actual motion vector predictors, the motion estimation is placed at the same macroblock stage as the rate-distortion mode analysis. The analysis is performed at the partition and macroblock levels. The reconstruction loop and the rate-distortion-optimization modules have the high throughput of 32 samples/coefficients per clock cycle, which enables the analysis of a significant number of preselected candidate modes. The high-throughput simplified rate estimation introduces slight quality losses and supports both entropy coding methods available in H.264/AVC. The average quality for the two coding methods is decreased by 0.07 and 0.17 dB compared to the JM17 software using the rate-distortion optimization. The compression efficiency can be traded for throughput. The architecture is verified in the real-time FPGA hardware encoder. Synthesis results show that the architecture consumes 551k gates and 148.63kB memories. It can support 1080p@60fps encoding for the 90nm TSMC technology.Index Terms-Video coding, H.264/AVC, FPGA, very largescale integration (VLSI) architecture 1051-8215 (c)

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Architecture of a Low Latency H.264/AVC Video Codec for Robust ML based Image Classification

Steinert

Stabernack

2022

J Sign Process Syst

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The use of neural networks is considered as the state of the art in the field of image classification. A large number of different networks are available for this purpose, which, appropriately trained, permit a high level of classification accuracy. Typically, these networks are applied to uncompressed image data, since a corresponding training was also carried out using image data of similar high quality. However, if image data contains image errors, the classification accuracy deteriorates drastically. This applies in particular to coding artifacts which occur due to image and video compression. Typical application scenarios for video compression are narrowband transmission channels for which video coding is required but a subsequent classification is to be carried out on the receiver side. In this paper we present a special H.264/Advanced Video Codec (AVC) based video codec that allows certain regions of a picture to be coded with near constant picture quality in order to allow a reliable classification using neural networks, whereas the remaining image will be coded using constant bit rate. We have combined this feature with the ability to run with lowest latency properties, which is usually also required in remote control applications scenarios. The codec has been implemented as a fully hardwired High Definition video capable hardware architecture which is suitable for Field Programmable Gate Arrays.

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A high throughput H.264/AVC intra-frame encoding loop architecture for HD1080p

Cited by 12 publications

References 11 publications

Intra Prediction for the Hardware H.264/AVC High Profile Encoder

Intra Prediction for the Hardware H.264/AVC High Profile Encoder

Architecture Design of the H.264/AVC Encoder Based on Rate-Distortion Optimization

Architecture of a Low Latency H.264/AVC Video Codec for Robust ML based Image Classification

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