A programmable 1400 MOPS video signal processor

Huizer, C.M.; Baker, K.; Mehtani, K.; Block, Jen; Dijkstra, Han J.; Hynes, P.J.; Lammerts, J.A.M.; Lecoutere, M.; Popp, Andreas; Roermund, Arthur van; Sheridan, Phil; Sluyter, R.J.; Welten, F.

doi:10.1109/cicc.1989.56824

Cited by 23 publications

(5 citation statements)

References 9 publications

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“…2) with 32 ports have a cycle time less than or equal to 3.41 ns, we would have required the consideration of design alternatives like further pipelining the network (by incorporating extra latches), considering a different kind of network, or redesigning the data-flow. It is to be noted that if the processors need to write back into memory or the memory addresses themselves are generated by the processors, unlike the proposed architecture, 11 thereby needing two-way communication between the memory and the processors, 16 PE's and 16 ME's would require a network which has 32 input ports and wraps around (as in the Philips chip [10]); we have not simulated such networks in our present work.…”

Section: A On-chip Memory Designmentioning

confidence: 90%

“…Since it is possible to meet the cycle time requirement with 8 8-b memory arrays, each memory bank can be built out of two such arrays where each array provides four of the required data bits for a pixel. 10 We will assume that all the memory banks are double buffered so that one half of the bank can be written into while the other half is being read-this, as explained later, will help us achieve a higher throughput. , only a pipelined multistage network with 16 ports gives a cycle time (2.81 ns) less than 3.41 ns.…”

Section: A On-chip Memory Designmentioning

confidence: 99%

“…The 1-D transform is defined as if otherwise (10) where are the pixel values. For our purposes, we assume that each 2-D DCT on an 8 8 input matrix is computed using 16 (eight rows followed by eight columns) 1-D DCT's.…”

Section: A Deciding On the Algorithmmentioning

confidence: 99%

“…This is certainly true for old technologies, but with today's advanced manufacturing technologies and novel circuit design techniques [18], it is possible to build a high-speed system based on Crossbars. In fact, some of today's video processors [10], [19] implement Crossbars to facilitate memory-processor communications.…”

Section: B Network Circuit Simulationmentioning

confidence: 99%

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A methodology to evaluate memory architecture design tradeoffs for video signal processors

Dutta

Wolf²,

Wolfe³

1998

IEEE Trans. Circuits Syst. Video Technol.

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This paper develops a methodology for the design of the memory and the memory-processor communication network in video signal processors. The memory subsystem is the bottleneck of most video computing systems and its design requires evaluating tradeoffs between area, cycle time, and utilization. We emphasize the need to consider technological and circuit-level issues during the design of a system architecture, particularly video signal processing (VSP) systems, and present a systematic method whereby the organization of the memory architecture-the granularity of memory partitioning and the size and type of interconnection network-can be analyzed and its cycle-time approximated before a detailed design is undertaken. We show how variations in sizes and circuit configurations help determine the variations in delay of both memory and network, and how the delay curves, thus determined, can be used to design, compare, and choose from different memorysystem architectures; we also describe a technique that can be used to identify the on-chip-off-chip boundary with respect to a hierarchical memory-system design for a memory-intensive VSP module. All of our results are validated via layout and simulation of prototype circuits in two different process technologies. Motion estimation and discrete cosine transform (DCT) being two of the most important tasks in video processing, we use the design of a motion estimator and that of a DCT unit as examples to illustrate the high-level issues in designing the memory architecture for a VSP module. The analysis presented for the motion estimator and the DCT unit can also be applied to other processing blocks belonging to the system. Index Terms-Circuit simulation, hierarchical memory architecture, memory bank conflict, multiport memory, multistage interconnection network.

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Section: A On-chip Memory Designmentioning

confidence: 90%

Section: A On-chip Memory Designmentioning

confidence: 99%

Section: A Deciding On the Algorithmmentioning

confidence: 99%

Section: B Network Circuit Simulationmentioning

confidence: 99%

See 2 more Smart Citations

A methodology to evaluate memory architecture design tradeoffs for video signal processors

Dutta

Wolf²,

Wolfe³

1998

IEEE Trans. Circuits Syst. Video Technol.

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“…By contrast, the schedule transformation uses one switch, one switch and one switch. The compositing processing and switching can be bundled into application specific ICs [11] [25].…”

Section: Performancementioning

confidence: 99%

Architectures for multi-source multi-user video compositing

Yun¹,

Messerschmidt²

1993

Proceedings of the First ACM International Conference on Multimedia - MULTIMEDIA '93

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Video compositing is the editing and integrating of many video images into a single presentation. Several single-user compositing systems have already been suggested, but the multiple users problem remains unstudied. We propose two new architectures for digital video compositing in a multi-user environment that are both memory-efficient and can operate in real-time. We show that under hard throughput and bandwidth constraints, a memoryless solution for transferring data from many video sources to many users does not exist. We overcome this using (i) a dynamic memory buffering architecture; and (ii) a constant memory bandwidth solution that transforms the sources-to-users transfer schedule into 2 schedules, then pipelines the computation. The architectures support opaque overlapping of images, arbitrarily shaped images, and images whose shapes dynamically change from frame to frame.

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On architectures for video compositing

Yun

Messerschmitt

1994

Multimedia Systems

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A programmable 1400 MOPS video signal processor

Cited by 23 publications

References 9 publications

A methodology to evaluate memory architecture design tradeoffs for video signal processors

A methodology to evaluate memory architecture design tradeoffs for video signal processors

Architectures for multi-source multi-user video compositing

On architectures for video compositing

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