A predictive bottom-up hierarchical approach to digital system reliability

Huard, V.; Pion, E.; Cacho, F.; Croain, Damien; Robert, V.; Delater, R.; Mergault, P.; Engels, Sylvain; Flatresse, Philippe; Amador, N. Ruiz; Anghel, Lorena

doi:10.1109/irps.2012.6241830

Cited by 29 publications

(9 citation statements)

References 5 publications

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“…This extrapolation is based on our analytical model (1)- (8) and on the composite model proposed in [20]. The latter provides a successful expression that well captures the mean dependence of the V t shift (μ V t ) on the stress voltage V gstress , temperature and stress time t stress .…”

Section: Bti Degradation At Operating Conditionsmentioning

confidence: 99%

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A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology

Husseini

Garros

Cluzel

et al. 2014

IEEE Trans. Electron Devices

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In this paper, we present for the first time a direct measurement procedure to characterize the bias temperature instability (BTI)-induced dynamic variability in static random access memory (SRAM) cells. This measurement procedure is based on the supply read retention voltage metric. The variability results obtained with this technique are explained by means of Monte Carlo SPICE simulations. The analytical model is then proposed to extrapolate this BTI-induced variability at different stress conditions. Finally, the impact of this variability on a large SRAM array is investigated. A semianalytical method is first developed to calculate the fresh read failure probability for different operating voltages V DD . The model is then extended to address the effect of BTI stress on the SRAM array. Results show that under SRAM cells operating conditions the bitcell read stability is barely impacted by BTI stress even after 10 years of work.Index Terms-Bias temperature instability (BTI) stress measurements, BTI stress modeling, read failure probability evaluation, static random access memory (SRAM) cells, supply read retention voltage (SRRV) metric.

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Section: Bti Degradation At Operating Conditionsmentioning

confidence: 99%

“…Ten years extrapolation of the V t degradation for PUR and PDL transistors at T = 25°C and V g = V DD using the composite model[20].…”

mentioning

confidence: 99%

A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology

Husseini

Garros

Cluzel

et al. 2014

IEEE Trans. Electron Devices

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“…Models, accurately regarding the influence of the mission scenario work at, or below, the transistor level and are thus far too slow for early prediction. Closest to our approach is [9], which can predict NBTI and Hot Carrier Injection (HCI)-based delay degradation over time, regarding stress and recovery times as well as temperature and voltage with a simple analytical approach. Their model results in an analytical equation with component age, temperature and voltage as scalar parameters.…”

Section: Related Workmentioning

confidence: 99%

Considering variation and aging in a full chip design methodology at system level

Helms

Grüttner

Eilers

et al. 2014

Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn)

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We present a new system-level design methodology enabling the consideration of process variations and degradation due to aging in early stages of the design process. By mapping an executable system specification to SoC processing, communication and memory components in combination with component wise timing and power characterization with a source-level backannotation, we enable efficient full SoC power and temperature over time simulations. Based on the resulting temporal and spatial power and temperature distribution we use a high-level multiphysics simulation to assess the impact of degradation and aging. We evaluate our approach using an ARM7 based SoC design.

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“…Even though the model itself is too simplistic, the authors propose a useful gate-netlist reduction technique, eliminating nodes, which are irrelevant for the circuits timing correctness. In [5], an abstract model for system level NBTI and HCD description is presented. It models NBTI with an extended RD model, called the composite model.…”

Section: Related Workmentioning

confidence: 99%

Efficient NBTI modeling technique considering recovery effects

Eilers

Metzdorf

Helms

et al. 2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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The aging effect "Negative Bias Temperature Instability", which is highly dependent on device history, has a direct impact on the design of integrated circuits. In order to make realistic predictions available in the design process, simulation durations of existing history aware models must be significantly reduced. Therefore, a performance-oriented, yet accurate abstraction of the switching trap NBTI model is presented within this paper. Evaluation results for various stress scenarios demonstrate very precise NBTI simulations and a major improvement to another performance-oriented model abstraction. Simulation durations facilitate realistic aging predictions of larger components in a reasonable period of time.

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A predictive bottom-up hierarchical approach to digital system reliability

Cited by 29 publications

References 5 publications

A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology

A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology

Considering variation and aging in a full chip design methodology at system level

Efficient NBTI modeling technique considering recovery effects

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