A Predictable Robust Fully Programmable Analog Gaussian Noise Source for Mixed-Signal/Digital ATE

Aouini, Sadok; Roberts, G.W.

doi:10.1109/test.2006.297677

Cited by 11 publications

(8 citation statements)

References 4 publications

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“…The resulting oversampling ratio (OSR) is set to 32. The DTC was constructed using a 90°phase step with a 50 % duty cycle so that the bit map replaces every 0 bit from the ΣΔ modulator with a 1100 code, and all subsequent 1's by a bit code of 0110 [2]. The DUT was implemented in hardware using a 6th-order PLL designed to approximate a Gaussian filter response.…”

Section: Discrete-implementation Of the Ptimentioning

confidence: 99%

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

Bielby

Chowdhury

et al. 2016

J Electron Test

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An instrument for on-chip measurement of transceiver transmission capability is described that is fully realizable in CMOS technology and embeddable within an SoC. The instrument can be used to inject and extract the timing and voltage information associated with signals in high-speed transceiver circuits that are commonly found in data communication applications. At the core of this work is the use of ΣΔ amplitude-and phase-encoding techniques to generate both the voltage and timing (phase) references, or strobes used for high-speed sampling. The same technique is also used for generating the test stimulant for the device-under-test.cloud computing, etc. In order to keep component costs down, low-cost test techniques are essential. One strategy is to incorporate test circuits directly on-chip to standardize test equipment access, improve accuracy and repeatability, and to contribute to short test times through parallel test procedures. In some cases, an on-chip instrument may be the only means to capture information associated with some internal core circuit. An important attribute of such on-chip test circuits is a low silicon area overhead. In addition, such on-chip instruments are not bandwidth limited by the test channel, so tests can be performed at the desired operating frequencies and speeds [7]. A software programmable, probabilistic test instrument using ΣΔ-encoded phase/amplitude-signal generators is to be described in this paper.This work in a shorter form was first presented at the 20th International Mixed-Signal Testing Workshop [14]. In that publication the general concept of the probabilistic instrument was proposed and demonstrated with discrete components. In this publication, our first attempt at integrating the concept into a 130 nm CMOS IC realization. The results of this endeavor will also be described here. While our intent is to use this instrument as part of an embedded instrument for high-speed transceivers, however, at this point in time, the IC results do not operate anywhere close to the 1 Gbps rates required by today's I/Os. This is not meant to be a definitive statement that the approach is not sound but rather the results gather here is a testament of the working principle. It is expected that future work will improve the operating speed and measurement resolution suitable for next generation transceiver ICs. This paper will begin with a system overview of the probabilistic test instrument (PTI) in Section II, including a description of various methods for phase and voltage signal generation using sigma-delta encoding methods, and CDF extraction. Section III will describe the critical decision-making circuits such as the D-type flip-flops and comparator circuits used in the CMOS IC implementation. Section IV will describe the Responsible Editors:

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Section: Discrete-implementation Of the Ptimentioning

confidence: 99%

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

Bielby

Chowdhury

et al. 2016

J Electron Test

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“…In fact, for a reference clock having a period T ref, a phase delay <l>dela y in degrees would result in a corresponding time delay tdela y given by (8) delay 36 00 ref Hence, a faster reference clock having a smaller period would result in a smaller time delay in seconds for the same delay in degrees. In other words, since the resolution of the sigma-delta modulation process is preserved in the phase domain, a faster clock would result in a smaller time range and a smaller time resolution.…”

Section: Phase Signal Generation Operationmentioning

confidence: 99%

“…Given that the maximum phase encoding delay is <1>1 and the minimum is <1>0, the corresponding maximum and minimum time delays t1 and to can be found from Eqn. (8). The following equation resolution tres is also made smaller to preserve an equivalent SNR, II -to rA -¢o SNR�t.…”

Section: Phase Signal Generation Operationmentioning

confidence: 99%

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A low-cost ATE phase signal generation technique for test applications

Aouini

Chuai

Roberts

2010

2010 IEEE International Test Conference

Self Cite

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In this article, an accurate and low-cost clock delay generation system integrated in an automated test equipment (ATE) environment is presented. The input to this system is entirely digital and is driven by a single clock, which can be programmed from the ATE High Speed Digital (HSD) unit. Moreover, the digital input patterns can easily be generated in software off-line; hence, making this system ideal for automated test routines. The system is first discussed and characterized in Matlab under static and dynamic operating conditions. For the static behavior, the impact of the various design tradeoffs on the time resolution is investigated. With regards to the dynamic behavior, the linearity is assessed spectrally with a sinusoidal input and statistically using a Gaussian noise signal. A discrete prototype board is built to validate the correct operation of the system mounted on an A TE to function as a whole. With proper compensation and calibration, a delay resolution of 15 ps was achieved over an 8.4 ns range using a low-speed reference clock running at 16.67 MHz. It is shown through clock scaling that this resolution can improve in direct proportion to increases in the clock frequency.

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“…In this paper, we present another type of power analysis side channel that can be exploited through software, potentially remotely. We show that ADC noise, which is usually characterized using statistical methods [LRRB05,Nat15,AR06], is not just statistical noise, but is correlated to the activity in the digital subsystem. To assess the capability of this side-channel, we perform leakage assessment [GGJR + 11, SM15] on multiple platforms.…”

Section: Introductionmentioning

confidence: 98%

Leaky Noise: New Side-Channel Attack Vectors in Mixed-Signal IoT Devices

Gnad

Krautter

Tahoori

2019

TCHES

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Microcontrollers and SoC devices have widely been used in Internet of Things applications. This also brings the question whether they lead to new security threats unseen in traditional computing systems. In fact, almost all modern SoC chips, particularly in the IoT domain, contain both analog and digital components, for various sensing and transmission tasks. Traditional remote-accessible online systems do not have this property, which can potentially become a security vulnerability. In this paper we demonstrate that such mixed-signal components, namely ADCs, expose a new security threat that allows attackers with ADC access to deduce the activity of a CPU in the system. To prove the leakage, we perform leakage assessment on three individual microcontrollers from two different vendors with various ADC settings. After showing a correlation of CPU activity with ADC noise, we continue with a leakage assessment of modular exponentiation and AES. It is shown that for all of these devices, leakage occurs for at least one algorithm and configuration of the ADC. Finally, we show a full key recovery attack on AES that works despite of the limited ADC sampling rate. These results imply that even remotely accessible microcontroller systems should be equipped with proper countermeasures against power analysis attacks, or restrict access to ADC data.

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A Predictable Robust Fully Programmable Analog Gaussian Noise Source for Mixed-Signal/Digital ATE

Cited by 11 publications

References 4 publications

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

A low-cost ATE phase signal generation technique for test applications

Leaky Noise: New Side-Channel Attack Vectors in Mixed-Signal IoT Devices

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