A power, packaging, and cooling overview of the IBM eServer z900

Singh, Prabjit; Ahladas, Steven; Becker, W.D.; Bosco, F. E.; Corrado, J. P.; Goth, G. F.; Iruvanti, Sushumna; Nobile, Matthew A.; Notohardjono, Budy; Quick, John; Seminaro, E. J.; Soohoo, K.M.; Wu, Chang‐Yu

doi:10.1147/rd.466.0711

Cited by 14 publications

(8 citation statements)

References 13 publications

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“…Effective heat removal achieved by this solution allows the system to operate the chipset at higher power densities with cooler chip junction temperatures than was previously possible. As an alternative to the WCU, customers can also obtain the modular refrigerant unit that has been used for chip cooling over several previous zSeries generations [4]. Figure 1(b) shows the detailed assembly structure of the CEC unit, which is similar to that of the z10 EC.…”

Section: Cec Components and System Logic Structurementioning

confidence: 99%

Electronic packaging of the IBM System z196 enterprise-class server processor cage

Strach

Bosco²,

Köbel³

et al. 2012

IBM J. Res. & Dev.

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In this paper, we describe the first-and second-level system packaging structure of the IBM zEnterprise A 196 (z196) enterprise-class server. The design point required a more than 50% overall increase in system performance (in millions of instructions per second) in comparison to its predecessor. This resulted in a new system design that includes, among other things, increased input/output bandwidth, more processors with higher frequencies, and increased current demand of more than 2,000 A for the six processor chips and two cache chips per multichip module. To achieve these targets, we implemented several new packaging technologies. The z196 enterprise-class server uses a new differential memory interface between the processor chips and custom-designed server memory modules. The electrical power delivery system design follows a substantially new approach using Vicor Factor Power A blocks, which results in higher packaging integration density and minimized package electrical losses. The power noise decoupling strategy was changed because of the availability of deep-trench technology on the new processor chip generation.

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Section: Cec Components and System Logic Structurementioning

confidence: 99%

Electronic packaging of the IBM System z196 enterprise-class server processor cage

Strach

Bosco²,

Köbel³

et al. 2012

IBM J. Res. & Dev.

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“…Another conclusion that can be derived from Table II is that as the data rate is increasing while the package latency remains unchanged, the source synchronous signaling is needed because TABLE II EVOLUTION OF IBM zSeries eServer SIGNAL INTERFACES TABLE III z990 NOISE BUDGET COMPARED TO THE z900 [1] the clock skew and jitter magnitude do not decrease proportionally with the data rate increases. Consequently, even more bits will be stored on the bus, and more sophisticated I/O circuits and logic are needed to reduce the intersymbol interference due to the reflections on the interconnect and reject jitter and noise.…”

Section: Z990 Signalingmentioning

confidence: 99%

“…This restriction limits both the size of the heat sink and the air flow rate. This challenge was met by employing as the primary cooling method for the z990 CEC cage the modular cooling unit (MCU) technology which was introduced in the G4 model of the zSeries e-servers [1]. 16 processor cores on the same node made such a cooling solution particularly cost effective by maintaining the junction temperature below 50 C, controlling the leakage current on both the processor and the L2 cache chips, and consequently significantly increasing the chips' sorting range and yield.…”

Section: Introductionmentioning

confidence: 99%

T-Rex, a blade packaging architecture for mainframe servers

Katopis

Becker

Harrer³

2005

IEEE Trans. Adv. Packag.

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In this paper, we describe the application of the blade packaging concept to the IBM zSeries eServer z990, code-named T-Rex. The advantages of such packaging architecture are highlighted and the challenges for the system performance are identified. The physical and electrical attributes of the five types of buses required to support a processing operating frequency of 1.25 GHz in a symmetric multiprocessing (SMP) architecture with up to 64 processor cores are tabulated. The evolution of the I/O circuits for each of these buses is described along with the bus cycle time and bandwidth trends.Index Terms-Blade servers, computer architecture, computer system design, design methodology, electronic packaging, high-frequency digital signals, mainframe computers, multichip modules (MCMs), semiconductor device packaging.

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“…The attributes of the z990 MCM have been added to a table from [6] shown here as Table 1. The areas of significant change are indicated with bullets in the 2003 z990 column.…”

Section: MCMmentioning

confidence: 99%

First- and second-level packaging of the z990 processor cage

Winkel

Becker²,

Harrer

et al. 2004

IBM J. Res. & Dev.

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In this paper, we describe the challenging first-and secondlevel packaging technology of a new system packaging architecture for the IBM eServer z990. The z990 dramatically increases the volumetric processor density over that of the predecessor z900 by implementing a super-blade design comprising four node cards. Each blade is plugged into a common center board, and a blade contains the node with up to sixteen processor cores on the multichip module (MCM), up to 64 GB of memory on two memory cards, and up to twelve self-timed interface (STI) cables plugged into the front of the node. Each glass-ceramic MCM carries 16 chips dissipating a maximum power of 800 W. In this super-blade design, the packaging complexity is increased dramatically over that of the previous zSeries eServer z900 to achieve increased volumetric density, processor performance, and system scalability. This approach permits the system to be scaled from one to four nodes, with full interaction between all nodes using a ring structure for the wiring between the four nodes. The processor frequencies are increased to 1.2 GHz, with a 0.6-GHz nest with synchronous double-data-rate interchip and interblade communication. This data rate over these package connections demands an electrical verification methodology that includes all of the different relevant system components to ensure that the proper signal and power distribution operation is achieved. The signal integrity analysis verifies that crosstalk limits are not exceeded and proper timing relationships are maintained. The power integrity simulations are performed to optimize the hierarchical decoupling in order to maintain the voltage on the power distribution networks within prescribed limits.

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A power, packaging, and cooling overview of the IBM eServer z900

Cited by 14 publications

References 13 publications

Electronic packaging of the IBM System z196 enterprise-class server processor cage

Electronic packaging of the IBM System z196 enterprise-class server processor cage

T-Rex, a blade packaging architecture for mainframe servers

First- and second-level packaging of the z990 processor cage

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