A Power-efficient Bidirectional Potentiostat-based Readout IC for Wide-range Electrochemical Sensing

Tsai, Jung‐Fa; Chen, Yi‐Chia; Liao, Yu-Te

doi:10.1109/iscas.2018.8351107

Cited by 14 publications

(2 citation statements)

References 17 publications

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“…A known issue in this CCO circuit is the limited linearity of the output frequency f CCO at high input currents [38]- [40]. This is due to the constant gate delay, t delay , between the time instance when the latch toggles up to the time instance when the current integration proceeds on a second capacitor.…”

Section: B Linearization Techniquementioning

confidence: 99%

“…The solutions proposed in literature range from restriction to low-frequency operation, where the delay is not dominant [40], to extensive digital post-processing using look-up tables [41], digital filters, or other feedback structures [39]. In an IMC system, these solutions would not be ideal, as they incur either significant area or latency penalties.…”

Section: B Linearization Techniquementioning

confidence: 99%

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HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Khaddam-Aljameh

Stanisavljević

Mas

et al. 2022

IEEE J. Solid-State Circuits

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We present a 256 × 256 in-memory compute (IMC) core designed and fabricated in 14-nm CMOS technology with backend-integrated multi-level phase change memory (PCM). It comprises 256 linearized current-controlled oscillator (CCO)-based A/D converters (ADCs) at a compact 4-µm pitch and a local digital processing unit (LDPU) performing affine scaling and ReLU operations. A frequency-linearization technique for CCO is introduced, which increases the maximum Manuscript

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Section: B Linearization Techniquementioning

confidence: 99%

Section: B Linearization Techniquementioning

confidence: 99%

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Khaddam-Aljameh

Stanisavljević

Mas

et al. 2022

IEEE J. Solid-State Circuits

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High accuracy potentiostat with wide dynamic range and linearity

Toprak

Vural

Batur

2021

AEU - International Journal of Electronics and Communications

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Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators

Rasch,

Mackin,

Le Gallo

et al. 2023

Nat Commun

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Analog in-memory computing—a promising approach for energy-efficient acceleration of deep learning workloads—computes matrix-vector multiplications but only approximately, due to nonidealities that often are non-deterministic or nonlinear. This can adversely impact the achievable inference accuracy. Here, we develop an hardware-aware retraining approach to systematically examine the accuracy of analog in-memory computing across multiple network topologies, and investigate sensitivity and robustness to a broad set of nonidealities. By introducing a realistic crossbar model, we improve significantly on earlier retraining approaches. We show that many larger-scale deep neural networks—including convnets, recurrent networks, and transformers—can in fact be successfully retrained to show iso-accuracy with the floating point implementation. Our results further suggest that nonidealities that add noise to the inputs or outputs, not the weights, have the largest impact on accuracy, and that recurrent networks are particularly robust to all nonidealities.

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A Power-efficient Bidirectional Potentiostat-based Readout IC for Wide-range Electrochemical Sensing

Cited by 14 publications

References 17 publications

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

High accuracy potentiostat with wide dynamic range and linearity

Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators

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A Power-efficient Bidirectional Potentiostat-based Readout IC for Wide-range Electrochemical Sensing

Cited by 14 publications

References 17 publications

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

High accuracy potentiostat with wide dynamic range and linearity

Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators

Contact Info

Product

Resources

About

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs