A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms

Abstract

In this paper, a cost-effective and power-aware IP core design for computing the MPEG4 SA-DCT/IDCT is proposed. The proposed IP core has been developed based on the concept of programmable processors to provide the flexibility in dynamically configuring the hardware. The techniques exploited include adder-based distributed arithmetic, common subexpression sharing, canonical signed digit (CSD) representation, and equipping interleaved RAM. The proposed IP core also possesses the feature of power-aware design flexibility allowing the trade-off of lower power consumption with less demand of data precision in developing its instruction library. This design has been realized based on a 0.35-mm CMOS technology and costs about 3100 gates with 32 words of RAM, which can achieve the real-time processing of the texture coding in MPEG4 SP@L3 and ACE@L2 codec system for the CIF video at 30 frames per second (fps).

Loeffler DCT accelerator for small portable devices

“…If the I/O precision is allowed to be 13 bits, then the PSNR value becomes at least 44.8 dB. The precision of the internal units can also be reduced further to decrease hardware usage at the cost of the PSNR values, as in [8]. The Verilog model of the proposed accelerator has been synthesized with Synplify, targeting for a Xilinx FPGA, XC7VX485T-2.…”

“…In this letter, we are interested in a Loeffler DCT accelerator that uses as few adders as possible and achieves the optimal throughput for small portable devices. With the distributed arithmetic scheme, implementing the multiplications using one adder is possible, as in [8]; however, the resultant design has long latency and low throughput.…”