Reconfigurable low power MPEG-4 texture decoder IP design

Lin, Chun-Liang; Chang, Hsiu-Cheng; Guo, Jiun-In; Chen, Kuan‐Hung

doi:10.1109/apccas.2004.1412715

Cited by 2 publications

References 8 publications

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Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications

Boutellier

Cevrero

Brisk

et al. 2009

2009 IEEE Workshop on Signal Processing Systems

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Handheld devices are expected to start using fine-grained ASIC accelerators to meet energy-efficiency requirements of increasingly complex applications, e.g., video decoding and reconfigurable radio. To avoid overhead, static multiprocessor schedules are preferable for orchestrating fine-grained accelerators. However, as modern applications use accelerators in irregular patterns, static scheduling leads to low hardware utilization.Run-time scheduling for fine-grained accelerators solves the utilization problem, but easily produces significant overhead. We propose an efficient Accelerator Management Unit (AMU) , implemented in hardware. E.g., in video decoding, the AMU takes 3 to 18 cycles to compute a macroblock decoding schedule. The CPU may perform useful work, as the AMU does independent task dispatching.Two experiments are performed, where the AMU is integrated into an FPGA-based multiprocessing prototype system. One experiment does AMU-orchestrated MPEG-4 video decoding and the other demonstrates that the AMU enables low-overhead dynamic scheduling and produces a significant performance advantage over static scheduling.

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Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications

Boutellier

Cevrero

Brisk

et al. 2009

2009 IEEE Workshop on Signal Processing Systems

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Architecture Design of Shape-Adaptive Discrete Cosine Transform and Its Inverse for MPEG-4 Video Coding

Hsu¹,

Lee²,

Chang

et al. 2008

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-This paper presents efficient VLSI architectures of the shape-adaptive discrete cosine transform (SA-DCT) and its inverse transform (SA-IDCT) for MPEG-4. Two of the challenges encountered during the exploitation of more efficient architectures for the SA-DCT and SA-IDCT are addressed. One challenge is to handle the architectural irregularity due to the shape-adaptive nature. The other one is to provide acceptable throughput using minimal hardware. In the algorithm-level optimization, this work exploits the numerical properties found in the transform matrices of various lengths, and derives a fine-grained zero-skipping scheme for the IDCT which can perform 22.6% more zero-skipping than the common vector-based coarse-grained zero-skipping scheme does. In the architecture-level design, the 1-D variable-length DCT/IDCT architectures designed on the basis of the numerical properties are proposed. An auto-aligned transpose memory that aligns the data of different lengths is also incorporated. In addition, a zero-index table is also included in the transpose memory to support the fine-grained zero-skipping in the SA-IDCT. The synthesized designs of the SA-DCT and SA-IDCT are implemented using UMC 0.18-m technology. The SA-DCT architecture has 26 635 gates, and its average cycle-throughput is 0.66 pixels/cycle, which is comparable to other proposed architectures. On the other hand, the SA-IDCT architecture has 29 960 gates, and its cycle-throughput is 6.42 pixels/cycle. While decoding for CIF@30FPS, the SA-IDCT is clocked at 0.7 MHz, and the power consumption is 0.14 mW. Both the throughput and power consumption of the proposed SA-IDCT architecture are an order better than those of the existing SA-IDCT architectures.Index Terms-Discrete cosine transform (DCT), MPEG-4, video coding, VLSI.

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Reconfigurable low power MPEG-4 texture decoder IP design

Cited by 2 publications

References 8 publications

Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications

Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications

Architecture Design of Shape-Adaptive Discrete Cosine Transform and Its Inverse for MPEG-4 Video Coding

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